Single bit-line 10T SRAM cell for low power and high SNM

Abstract

Memories are the integral part of digital circuits thus power consumption of memory should be kept in consideration while designing the circuits. Memories should consume less power to improve system performance, stability, and efficiency. Earlier standard CMOS 6T SRAM cell was used which has two bit lines and a word line for both read and write operation. During the read operation stability decreases as the voltage is divided between access and driver transistors. In this paper new 10T SRAM with dynamic feedback control is proposed, which uses single bit line for both read and write operation. Power consumption reduces as single bit line is used and for both read and write operation and stability increases when compared with standard 6T SRAM. Proposed cell also show high static noise margin (SNM). The proposed 10T SRAM when compared with conventional 6T SRAM in terms of power consumed, delays, and SNM. The proposed 10 SRAM cells consume 83.27 % less power for write ‘0’ operation, 85.9 % less power for write 1 operation and delay increase for proposed 10T SRAM cell when compared with standard 6T SRAM cell. The proposed cell has 4.9 times SNM when compared with 6T SRAM. Using Cadence Virtuoso ADE with 180nm technology is used to draw schematics and simulation is carried out.