Single bit-line 7T SRAM cell for low power and high SNM

Abstract

Memories are integral parts of most of the digital devices and hence reducing power consumption of memory is very important in improving the system performance, efficiency and stability. Most of the embedded and portable devices use SRAM cells because of their ease of use as well as low standby leakage. Standard CMOS 6T SRAM cell uses two bit-lines and a word line for both read and write operations. This 6T SRAM cell consumes more power and shows poor stability at small feature sizes with low power supply. During read operation, the stability drastically decreases due to the voltage division between the access and driver transistors. In this paper new 7T SRAM cell is proposed, which uses single bit-line for both read and write operations. Power consumption is reduced because of single bit line usage and read stability is very high compared to conventional 6T SRAM cell. Proposed cell also provides high static noise margins (SNMs). The proposed 7T SRAM cell is compared with conventional 6T SRAM cell in terms of power consumed, delay and SNMs. The Proposed 7T SRAM cell consumes 22.03% less power for write ‘0’ operation, 17.33% less power for write ‘1’ operation, 17.52% less power for read ‘0’ operation and 21.36% less power for read ‘1’ operation compared to conventional 6T SRAM cell. The proposed cell has 2.64 times SNM in read state; 1.082 times SNM in hold state and 1.064 times SNM in write 0 state compared to conventional 6T SRAM cell. Schematics are drawn using virtuoso ADE of Cadence, and all simulations are carried out using Cadence Spectre Analyzer with 90nm Technology library at 1.8V VDD.