Abstract
An innovative and stable PNN based 10-transistor (10T) static random-access memory (SRAM) architecture has been designed for low-power bit-cell operation and sub-threshold voltage applications. The proposed design belongs to the following features: (a) pulse control based read-assist circuit offers a dynamic read decoupling approach for eliminating the read interference; (b) we have utilized the write data-aware techniques to cut off the pull-down path; and (c) additional write current has enhanced the write capability during the operation. The proposed design not only solves the half-selected problems and increases the read static noise margin (RSNM) but also provides low leakage power performance. The designed architecture of 1-Kb SRAM macros (32 rows × 32 columns) has been implemented based on the TSMC-40 nm GP CMOS process technology. At 300 mV supply voltage and 10 MHz operating frequency, the read and write power consumption is 4.15 μW and 3.82 μW, while the average energy consumption is only 0.39 pJ.
Highlights
The static random-access memory (SRAM) occupies a large amount of layout area in the system on chip (SoC)
The SoC may classify into two categories: highspeed and low-power consumption
For robust subthreshold operation, we proposed a SRAM bit-cell design and employed pulse robust subthreshold operation, we proposed a SRAM bit-cell design and employed pulse control read-assist circuit, as well as write data-aware schemes to cut off the pull-down control read-assist circuit, as well as write data-aware schemes to cut off the pull-down channel for improving the write ability and eliminating read error without any boost circhannel for improving the write ability and eliminating read error without any boost circuit cuit when keeping transistor-count in 10
Summary
Publisher’s Note: MDPI stays neutral with regard to jurisdictional claims in published maps and institutional affiliations. Many SRAM bit-cell design [9,10,11,12,13,14,15,16,17,18,19,20,21,22] have been presented to enhance circuit stability for robust low voltage/power operation. The problem of data contention (cross-coupled inverter structure) still exists These designs need additional write assist techniques to Sensors 2021, 21, 6591 to overcome this problem, a word line boost circuit technology to improve the write. These designs need additional write assist techniques to improve write margin [18,19].
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