Design of 10T SRAM cell for high SNM and low power

Abstract

Objective: In this paper, a 10-T (Transistor) static random access memory (SRAM) cell with reduced power and with improved static noise margin (SNM) is proposed. The 10-T SRAM employs a single bitline with dynamic feedback control which enhances the SNM at ultra low power. Further, the power consumption is trimmed down by the use of sleep transistors. The experimental results shows that the proposed 10T SRAM cell achieves SNM of 2.91x as that of conventional 6T SRAM and it has achieved 20.49% power reduction that of the 8T SE dynamic feedback loop using 45nm process.