Word Line Research Articles

Dielectric Engineering to Suppress Cell-to-Cell Programming Voltage Interference in 3D NAND Flash Memory.

In contrast to conventional 2-dimensional (2D) NAND flash memory, in 3D NAND flash memory, cell-to-cell interference stemming from parasitic capacitance between the word-lines (WLs) is difficult to control because the number of WLs, achieved for better packing density, have been dramatically increased under limited height of NAND string. In this context, finding a novel approach based on dielectric engineering seems timely and applicable. This paper covers the voltage interference characteristics in 3D NAND with respect to dielectrics, then proposes an alternative cell structure to suppress such interference.

Data Pattern Aware Reliability Enhancement Scheme for 3D Solid-State Drives

3D charge-trap (CT) NAND flash-based SSD has been used widely for its large capacity, low cost per bit, and high endurance. One-shot program (OSP) scheme, as a variation of incremental step pulse programming (ISPP) scheme, has been employed to program data for CT flash, whose program unit is the Word-Line (WL) instead of the page. The existing program optimization schemes either make trade-offs among program latency and reliability by adjusting the program step voltage on demand; or remap the most error-prone cell states to others by re-encoding programmed data. However, the data pattern, which represents the ratio of 1s in data values, has not been thoroughly studied. In this paper, we observe that most small files do not contain uniform 1s and 0s among these common file types (i.e., image, audio, text, executable file), leading to programming WL cells in different states unevenly. Some cell states dominate over the WL, while others are not. Based on this observation, we propose a flexible reliability enhancement scheme based on the OSP scheme. This scheme programs the cells into different states with varied , i.e., these cells in one state, whose number is the largest in one WL, are programmed with a fine-grained (namely slow write). In contrast, the minority are programmed with a coarse-grained (namely fast write). So the reliability is improved due to averaging the major enhanced cells with the minor degraded cells without program latency overhead. A series of experiments have been conducted, and the results indicate that the proposed scheme achieves 34% read performance improvement and 16% lifetime elongation on average.

Two-Direction In-Memory Computing Based on 10T SRAM With Horizontal and Vertical Decoupled Read Ports

In-memory computing establishes a new and promising computing paradigm aimed at solving problems caused by the von Neumann bottleneck. It eliminates the need for frequent data transfer between the memory and processing modules and enables the parallel activation of multiple lines. However, vertical data storage is generally required, increasing the implementation complexity for the SRAM writing mode. This article proposes a 10-transistor (10T) SRAM to omit vertical data storage and improve the stability of in-memory computing. A cross-layout of the word line enables arrays with multirow or multicolumn parallel activation to perform vector logic operations in two directions. In addition, the novel horizontal read channel allows matrix transposition. By reconfiguring the data lines, sense amplifiers, and multiplexing read ports, the proposed SRAM can be regarded as a content-addressable memory (CAM), and its symmetry provides selectable data search by column or by row according to the application that easily fits the SRAM storage mode without additional data adjustments. A proposed self-termination structure aims to decrease search energy consumption by approximately 38.5% at 0.9 V at the TT process corner. To verify the effectiveness of the proposed design, a 4 Kb SRAM was implemented in 28-nm CMOS technology. The read margin of the proposed 10T SRAM cell is three times higher than that of the conventional 6-transistor cell. At 0.9 V, logic operations can be performed at approximately 300 MHz, and binary CAM search operations are achieved at approximately 260 MHz with around 1 fJ of energy consumption per search/bit.

A Comprehensive Study of Nanosheet and Forksheet SRAM for Beyond N5 Node

SRAM bitcell area reduction, lower SRAM parasitic resistance, and higher drive strength are necessary to continue with technology scaling. Nanosheet (NSH) technology improves SRAM cell write-ability by having 50 mV more write trip point (WTP) than FinFET (FF) SRAM due to reduced bit line (BL) resistance (due to wider metal CD) and more drive current strength (more than 15%) than FF for the same leakage. However, due to higher bitcell area (20% larger), BL, and word line (WL) parasitic capacitance than FF, NSH SRAM would not compete with FF SRAM in terms of the read delay (26% more delay) and energy at the 3-nm technology node. PFET to NFET (PN) spacing, composed of gate cut, gate extension, and Fin pitch in an SRAM bitcell, is critical for SRAM cell height because it can take ~46% of the 111 SRAM total cell height. The forksheet (FSH), achieving extremely scaled PN space in SRAM bitcell due to device structure with limited additional processing complexity, reduces the SRAM bitcell area. As a result, BL and WL parasitics reduce and improve the SRAM read delay and stability. FSH SRAM saves 6% area benefit and achieves 24% lesser read delay than FF high density (HD) SRAM.

Cascade Current Mirror to Improve Linearity and Consistency in SRAM In-Memory Computing

Although multirow read is essential to achieve static random access memory (SRAM) in-memory computing (IMC), it may undermine circuit linearity and computational consistency across columns. In this study, we investigated the causes of nonlinearity and inconsistency. Based on detailed analyses, we proposed a cascade current mirror (CCM) peripheral circuit. Only four transistors were added to each bitline (BL) for voltage clamping and proportionally mirroring the read current. In addition, a 6T SRAM cell with double word lines operating with the CCM further reduced the delay and improved the computational consistency. We applied the structure to numerous prior studies and evaluated them using the 28-nm complementary metal-oxide semiconductor process. The measurement results show that the proposed CCM can reduce the integer nonlinearity by up to 70% at 0.8-V supply, and the computational consistency is substantially improved by 56.84% at 0.9-V supply. In addition, we verified the performance improvement through classification using a convolutional neural network, achieving 91% accuracy in the MNIST and 86% accuracy in the CIFAR-10. The area overhead was 1.77% in a 512×512 SRAM array when integrating the proposed CCM circuit.

On-chip weak resistive defect diagnosis with performance enhancement in 45 nm technology static random access memory

Rapid advancement in deep submicron technology has resulted in the highest occupancy of memory on system-on-chip. The impact of process variations has increased with advanced technology in scaled devices. The reliability of the system majorly depends on embedded memory in the system. But the testing of recent Static Random Access Memory (SRAM) has become significantly difficult with advanced device scaling technology. The unavoidable flaws during fabrication and also the effect of process variations lead to resistive open defects in SRAM cells that change the cell behavior as well as impacts the capability of the fault detection scheme implemented on the system. The detection of weak resistive defects is becoming difficult in advanced technology memory devices. For reliable operation of the system, effective testing technology needs to be implemented for maximum coverage of defects in memory. This work proposes built-in circuitry integrated with SRAM to increase the resistive defect coverage and reduces separate testing circuit requirements. This paper evaluates the effectiveness of the proposed resistive defect detection technique, which uses a predischarged bit line with variable word line stress. Analysis of resistive defect detection by the proposed method is performed on a wide range of resistive open defects introduced at random locations in the memory, with the effects of parasitic components are also investigated for the detection of weak resistive defects. The proposed method implemented on 1 KB of memory provides a minimum area overhead of 3.87 % and the least penalty of 20.48 μs.

Design of Low Power and Failure Free SRAM Cell Using Read Assist Circuits

Static Random Access Memory (SRAM) is one of the main peripherals in all the Very-large-scale Integrated (VLSI) chips, which enact a vital part in all executable applications. The write ability and read stability are prime factors with low power supply and improve operation speed with temperature, process, and voltage variations. In VLSI design, the System on Chip (SoC) performance is improved by applying low power supply and change in few Pico seconds of cycle times or memory access. The read/write operation is not accurate in lower supply voltage because it will not flip to the desired voltage levels. For improving performance, proposed an SRAM cell to flip to the desired voltage levels to reduce readability failures in low supply voltages. The additional requirement is needed to increase the chip’s performance with lower supply voltages, and continuously additional circuit techniques are needed for obtaining the SRAM memory’s readability and writing ability. In this paper, different performance improvement methods of SRAM memory cells are analyzed. The reduced word line voltage read assist circuit is designed for the SRAM memory cell.

Monolithic and single-functional-unit level integration of electronic and photonic elements: FET-LET hybrid 6T SRAM

A broad range of technologies have been developed for the chip and wafer scale connections and integrations of photonic and electronic circuits, although major challenges remain for achieving the single-functional-unit-level integration of electronic and photonic devices. Here we use field-effect transistor/light-effect transistor (FET–LET) hybrid 6T static random-access memory (SRAM) as an example to illustrate a novel approach that can alleviate three major challenges to the higher-level integration of the photonic and electronic elements: size mismatch, energy data rate, and cascadability. A hybrid 6T SRAM with two access FETs being replaced by LETs and the electrical word lines replaced by optical waveguides is proposed. This hybrid 6T SRAM is analyzed to reveal its potential in improvement of the switching speed and thus total energy consumption over the conventional 6T SRAM. Numerical analyses, for instance, for a prototype 64 kB hybrid SRAM array, show a factor of 4 and 22 reduction in read delay and read energy consumption, and 3 and 4 in write delay and write energy consumption, respectively, when the access FETs are replaced by LETs. The potential impacts on the peripheral and assist circuits due to this hybrid structure and application of the LETs there are also briefly discussed.

Design and implementation of Dual-Port Memory

Multiport memory cell using a dual-port memory cell provides required access to multi-processor-based applications. Simultaneous access can be provided using two-pass transistors, pair of bit lines, and a word line. Using specific word lines and bit lines of SRAM cell access can be provided by using dual ports memory. The single address of a memory cell can be accessed at a time during each clock pulse using single-port SRAM this drawback can be overcome by using dual-port RAM which supports concurrent read or writes access at different addresses. Efficiency is improved by using dual-port RAM. Each processor can be made to operate at different clock frequencies thereby dual-port RAM will not have any limitations of access between the two ports.

Pre-Emphasis Pulse Design for Random-Access Memory

This paper describes how one can reduce the memory access time with pre-emphasis (PE) pulses even in non-volatile random-access memory. Optimum PE pulse widths and resultant minimum word-line (WL) delay times are investigated as a function of column address. The impact of the process variation in the time constant of WL, the cell current, and the resistance of deciding path on optimum PE pulses are discussed. Optimum PE pulse widths and resultant minimum WL delay times are modeled with fitting curves as a function of column address of the accessed memory cell, which provides designers with the ability to set the optimum timing for WL and BL (bit-line) operations, reducing average memory access time.

Comparative Analysis of the Design Techniques for Low Leakage SRAMs at 32nm

This paper presents a comprehensive overview of leakage reduction techniques prevailing in Static Random Access Memories (SRAMs) by classifying them in three categories namely latch, bitline and read port. The performance of the techniques are evaluated in terms of leakage reduction capability along with the impact on read performance and hold stability through extensive simulative investigations at 32 nm technology node by taking conventional SRAM cell as reference. Further, as SRAMs are susceptible to inter-die as well as intra-die process variations, the performance at different PVT corners is also captured to demonstrate the efficacy of each technique under PVT variations. It is found that among the techniques used for reducing latch leakages, Multi-threshold CMOS technique possess the highest leakage reduction capabilities followed by Drowsy mode and Substrate-bias techniques. The results also indicate that Negative word line technique is more effective at low supply voltages whereas the Leakage biased bitline technique is more effective at high supply voltages for reducing bitline leakages. Amongst the read port leakage reduction techniques, Stack-effect and Dynamic control of power supply rail techniques are capable of suppressing the leakages at high voltages whereas Virtual cell ground technique is more efficacious at low voltages. The impact of technology scaling on SRAM cell performance with leakage reduction techniques is also studied. For the sake of completeness, suggestions are put forward for adopting a particular technique to address leakages at latch, bitline and read port levels.

Reducing Thickness Deviation of W-Shaped Structures in Manufacturing DRAM Products Using RSM and ANN_GA

Thickness deviation on a W-shaped structure of word lines in dynamic random access memories (DRAMs) is detrimental to the DRAM manufacturing's yield rate. The case company has suffered from a low yield rate in their DRAM manufacturing due to large thickness deviations on the W-shaped structures. This article proposed a new approach to find an appropriate setting of manufacturing control factors' values to decrease the thickness deviation. In the proposed method, we first used the fractional factorial design to select important control factors related to the thickness deviation. We then used the gradient descent method to find a region of control factors that contained a second-order solution to the problem and adopted the response surface method (RSM) to find the second-order solution. However, the second-order RSM was limited by its second-order relationship between the input control factors and the output thickness deviation. To further reduce the thickness deviation, we used an artificial neural network (ANN) to predict the thickness deviation given a set of control factors' input values. We then used a genetic algorithm (GA) to find a better solution to the problem with the predicted thickness deviations by the ANN. The confirmation experiment showed that the GA had found a better solution than the RSM method. With the proposed GA method, the case company has successfully reduced the thickness deviation from 45.0 to 12.9 Å, saving U.S. $205 000 per year on their DRAM manufacturing cost.

A Comparative Syntactic Typological Study of Iranian Languages: A case of Persian and Kurdish

Iranian dialects are subgroups of Indo-Iranian dialects and are arranges dependent on their course of events and locale. All Iranian dialects of the center and current occasions have some normal highlights. The plain word request is generally action word last, and the time framework depends on two action word lines, present and past, no matter what. While the current stem proceeds with the Old Iranian present that was acquired straightforwardly from Indo-European, the previous stem depends on a participatory type of the action word finishing off with – ta. The Iranian dialects are probably going to be spoken by in excess of 80 million individuals in a wide zone from Turkey with Zaza as the westernmost to China with Sarikoli as the western that the easternmost Iranian language and primarily cover the entirety of Iran, Afghanistan and Tajikistan. The advancement of the Iranian dialects can be analyzed in three significant chronicled periods: Old Iranian (up to the fourth/third century BC), Central Iranian (from the fourth/third century BC to the eighth/ninth century AD) and new Iranian language (since 900 AD). Two of the antiquated Iranian dialects are known and archived, Avestan and Old Persian. The Central Iranian dialects (approx. 300 BC – AD 950) are significantly more various. They are partitioned into two principle gatherings, western and eastern. Current Iranian dialects fall into two enormous “Eastern” and “Western” gatherings, with “Northern” and “Southern” sub-gatherings, separately. The qualification between the eastern and western Iranian dialects lies in the fundamental geological dispersion of the principle speakers of these dialects in the east or west of Lut deserts in Iran.

Integrating Two Logics Into One Crossbar Array for Logic Gate Design

Memristor-based crossbar array is one of the most promising structure for in-memory computing platforms. In a crossbar array, material implication logic (IMPLY) can be performed between different word lines or bit lines. Not-material implication (N-IMPLY) can only be performed between the bit lines. This brief demonstrates the feasibility of the execution of N-IMPLY logic between the word lines, followed by an approach for logic gate design in which two logics IMPLY and N-IMPLY are integrated into one crossbar array. Both two logics can be performed between the cells in different rows and columns within the crossbar. Six basic Boolean gates are implemented utilizing the proposed approach, with a lower number of operation steps and memristors compared to the IMPLY-only method. Moreover, a 1-bit full adder is implemented by utilizing the designed logic gates. The performance and area overhead have been improved by the proposed approach, in comparison to the existing methods.

Design and modeling of niobium oxide-tantalum oxide based self-selective memristor for large-scale crossbar memory

Memristor-based crossbar architecture has emerged as a promising candidate for 3-D memory, logic, and neuromorphic computing system as it offers remarkably high integration density, low power consumption, fast operation, and easy integration with CMOS technology. However, the fundamental obstacle for their development is the sneak current, which causes misreading and write-crosstalk. In this regard, we present the TiN/NbO2/TiN/TaOx/TiN based self-selective memristor by combining the threshold switching properties of niobium oxide (NbO2) and memory switching properties of tantalum oxide (TaOx) in a single device. The performance investigation is carried out using the finite element simulation method, based on self-consistent solutions of joule heating equation, drift-diffusion continuity equation, and current continuity for accurately capturing the temperature and field-dependent transport of vacancies. The results reveal that NbO2-TaOx based self-selective memristor can allow significantly lower OFF current (1.22 μA), higher read window (32.6), and higher non-linearity (141) than that of TiN/TaOx/TiN based memristor. We demonstrate that the self-selective memristor exhibits good speed with the operation time constant of 70 ns. Furthermore, the crossbar array using a self-selective memristor has shown excellent performance with an improved readout margin up to 27 word lines. Our material-to-circuit performance analysis promises a reliable and energy-efficient crossbar array using NbO2-TaOx cell that can be further utilized for implementing 3-D cross-bar array.

Single‐ended half‐select disturb‐free 11T static random access memory cell for reliable and low power applications

SummaryThis paper presents an 11 transistor (SEHF11T) static random access memory (SRAM) cell with high read static noise margin (RSNM) and write static noise margin (WSNM). It eliminates the write half‐select disturb using cross‐point data‐aware write word lines, which can mitigate bit‐interleaving structure to reduce multiple‐bit upset and increase soft‐error immunity. We evaluated and analyzed the effect of process, voltage, and temperature (PVT) variations on various design metrics and compared it with other cells. The SEHF11T performs fast read operation due to its higher read current and slow write operation due to its single‐ended nature. It employs the read decoupling technique to enhance the RSNM. The stacked transistors in the left/right half‐cell increase the RSNM. In addition, the WSNM is improved by eliminating the feedback of cross‐coupled inverters pair during write operation by means of power‐cutoff write‐assist technique. The proposed cell shows 1.11X higher RSNM and 1.37X higher WSNM compared to fully differential 8T (FD8T) cell. The stacked transistors in the cell reduce leakage power dissipation. The SEHF11T consumes 0.47X lower leakage power compared to FD8T at VDD = 0.7 V. Furthermore, it exhibits high reliability against PVT variations in subthreshold region and shows 1.09X narrower spread in leakage power than that of FD8T at VDD = 0.3 V.

Influence of Common Source and Word Line Electrodes on Program Operation in SuperFlash Memory

A theoretical study of the influence of word line and common source electrodes on the program operation in shrank SuperFlash memory is proposed. Numerical simulations demonstrate that the literature model defined for previous nodes is not always suitable, due to the continuous cell physical size reduction and to the consequent increment of capacitive coupling between the floating gate and adjacent electrodes. To get a deeper insight, an analytical model of the electric field in the region of source side injection is proposed. This model describes the impact of the cell physical and electrical parameters on the vertical and horizontal field components and highlights the strong dependence of the carrier injection on the technology node. Furthermore, the numerical and analytical models estimate the influence of the word line and common source electrodes on the time-to-program, the floating gate potential and the source side injection efficiency, taking into consideration, at the same time, their possible impact on the cell reliability.

An 8T SRAM Array with Configurable Word Lines for In-Memory Computing Operation

In-memory computing (IMC) has been widely accepted to be an effective method to improve energy efficiency. To realize IMC, operands in static random-access memory (SRAM) are stored in columns, which contradicts SRAM write patterns and requires additional data movement. In this paper, an 8T SRAM array with configurable word lines is proposed, in where the operands are arranged in rows, following the traditional SRAM storage pattern, and therefore additional data movement is not required. The proposed structure supports three different computing modes. In the ternary multiplication mode, the reference voltage generation column is not required. The energy of computing is only 1.273 fJ/bit. In the unsigned multibit multiplication mode, discharge and charging paths are used to enlarge the voltage difference of the least significant bit. In the logic operation mode, different types of operations (e.g., IMP, OR, NOR, XNOR, and XOR) are achieved in a single cycle. The frequency of logic computing is up to 909 MHz.

Surround Gate Transistor With Epitaxially Grown Si Pillar and Simulation Study on Soft Error and Rowhammer Tolerance for DRAM

A new dynamic random access memory (DRAM) memory cell transistor is fabricated, and its soft-error immunity and rowhammer tolerance are studied. The vertical channel is formed by selective epitaxial growth of silicon pillar, and the surround gate forms a fully depleted (FD) channel, which can suppress floating-body effects, such as hysteresis. A TCAD simulation study compares this device and conventional bulk saddle FinFET in terms of soft error immunity and rowhammer tolerance. The confined channel limits soft error because of its thin channel volume for charge generation due to alpha and neutron particles. The surround gate device is inherently free from rowhammer attack as each silicon body of any memory cell transistor is fully isolated from neighboring word lines.

Design of Dynamic Random Access Memory Based on One Transistor One Diode Memory Cell

This paper presents the design analysis of Dynamic Random Access Memory (DRAM) with one transistor one diode (1T1D). The proposed structure consists of one transistor and one voltage controlled diode capacitor. The word and bit lines are connected with two voltage sources for the write operation. The source and drain of the NMOS is tied together to form the diode structure. The off-state leakage current is the main cause for the power dissipation of DRAM. Thus the improvement of power efficiency to the overall system is a critical task. The conventional DRAM cell contains one capacitor and one transistor. But the absence of capacitor in the proposed work is advantageous by means of compatibility, scalability, fabrication complexity, and cost. Tanner EDA working platform of 7 nm technology is used for the implementation of 1T1D DRAM cell in proposed work. This work achieve the power dissipation, read and write access time in the range of 2.647 mW, 0.04 μs and 0.021 μs respectively. Also, the parameter comparison is performed by changing the technologies from 10 nm to 20 nm for 1T1D DRAM cell design.