Design of Low Power and Failure Free SRAM Cell Using Read Assist Circuits

Abstract

Static Random Access Memory (SRAM) is one of the main peripherals in all the Very-large-scale Integrated (VLSI) chips, which enact a vital part in all executable applications. The write ability and read stability are prime factors with low power supply and improve operation speed with temperature, process, and voltage variations. In VLSI design, the System on Chip (SoC) performance is improved by applying low power supply and change in few Pico seconds of cycle times or memory access. The read/write operation is not accurate in lower supply voltage because it will not flip to the desired voltage levels. For improving performance, proposed an SRAM cell to flip to the desired voltage levels to reduce readability failures in low supply voltages. The additional requirement is needed to increase the chip’s performance with lower supply voltages, and continuously additional circuit techniques are needed for obtaining the SRAM memory’s readability and writing ability. In this paper, different performance improvement methods of SRAM memory cells are analyzed. The reduced word line voltage read assist circuit is designed for the SRAM memory cell.