On-chip weak resistive defect diagnosis with performance enhancement in 45 nm technology static random access memory

Abstract

Rapid advancement in deep submicron technology has resulted in the highest occupancy of memory on system-on-chip. The impact of process variations has increased with advanced technology in scaled devices. The reliability of the system majorly depends on embedded memory in the system. But the testing of recent Static Random Access Memory (SRAM) has become significantly difficult with advanced device scaling technology. The unavoidable flaws during fabrication and also the effect of process variations lead to resistive open defects in SRAM cells that change the cell behavior as well as impacts the capability of the fault detection scheme implemented on the system. The detection of weak resistive defects is becoming difficult in advanced technology memory devices. For reliable operation of the system, effective testing technology needs to be implemented for maximum coverage of defects in memory. This work proposes built-in circuitry integrated with SRAM to increase the resistive defect coverage and reduces separate testing circuit requirements. This paper evaluates the effectiveness of the proposed resistive defect detection technique, which uses a predischarged bit line with variable word line stress. Analysis of resistive defect detection by the proposed method is performed on a wide range of resistive open defects introduced at random locations in the memory, with the effects of parasitic components are also investigated for the detection of weak resistive defects. The proposed method implemented on 1 KB of memory provides a minimum area overhead of 3.87 % and the least penalty of 20.48 μs.