Abstract
In contrast to conventional 2-dimensional (2D) NAND flash memory, in 3D NAND flash memory, cell-to-cell interference stemming from parasitic capacitance between the word-lines (WLs) is difficult to control because the number of WLs, achieved for better packing density, have been dramatically increased under limited height of NAND string. In this context, finding a novel approach based on dielectric engineering seems timely and applicable. This paper covers the voltage interference characteristics in 3D NAND with respect to dielectrics, then proposes an alternative cell structure to suppress such interference.
Highlights
NAND flash memory data storage has been developed for decades based on CMOS
NAND flash consists of memory cells and peripheral circuits
NAND flash is categorized as non-volatile memory (NVM)
Summary
NAND flash memory data storage has been developed for decades based on CMOS (complementary metal-oxide-semiconductor) technology [1]. NAND flash consists of memory cells and peripheral circuits. Device structure of a memory cell is based on NMOS transistors, which inherently contain charge trap layers (CTL) such as Si3 N4 in the gate dielectric. When positive bias (typically higher than 10 V) is applied to a gate electrode of a cell transistor to trigger ‘programming’, electrons are moved from the channel to the CTL by FN tunneling mechanism. In this context, the number of electrons stored in the CTL fundamentally represents the size of the binary data
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