Abstract
In-memory computing (IMC) has been widely accepted to be an effective method to improve energy efficiency. To realize IMC, operands in static random-access memory (SRAM) are stored in columns, which contradicts SRAM write patterns and requires additional data movement. In this paper, an 8T SRAM array with configurable word lines is proposed, in where the operands are arranged in rows, following the traditional SRAM storage pattern, and therefore additional data movement is not required. The proposed structure supports three different computing modes. In the ternary multiplication mode, the reference voltage generation column is not required. The energy of computing is only 1.273 fJ/bit. In the unsigned multibit multiplication mode, discharge and charging paths are used to enlarge the voltage difference of the least significant bit. In the logic operation mode, different types of operations (e.g., IMP, OR, NOR, XNOR, and XOR) are achieved in a single cycle. The frequency of logic computing is up to 909 MHz.
Highlights
Configurable Word Lines for Artificial intelligence and machine learning are highly valued technologies that are widely used in various fields [1]
We considered B = 1, C = 1 and B = 1, C = 0 as examples to introduce the process of XNOR/NOR
Due to the logic and ternary multiplication should be achieved on 0.5VDD bitline voltage, we evaluated the Pseudo-read static noise margin (SNM)
Summary
Configurable Word Lines for Artificial intelligence and machine learning are highly valued technologies that are widely used in various fields [1]. Khwa et al [3] used a six transistor (6T) cell combined with a reference voltage generation column to achieve ternary multiplication; Yin et al [4] proposed a 12T cell combined with a PMOS substrate offset to complete the same function In these methods, an additional area is required to realize a reference voltage generation array or the PMOS body bias. The operands of the operations mentioned above are stored in columns [2,3,4,5,8,10,11], which is different from that in the traditional static random-access memory (SRAM), where they are stored in rows, and they require additional data movement. We propose an 8T cell array to enable ternary multiplication, unsigned multibit multiplication, and Boolean logic operations of three operands.
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