Design of low leakage SRAM bit-cell and array

Abstract

There is an ever increasing need for running various multimedia and computer based applications on a variety of popular digital systems. These applications continue to become increasingly power-hungry and require critical performance levels. To achieve the required benchmark performance, devices have to employ high speed processors in addition to low power on-chip memory. As the power consumed during memory access accounts for a considerable portion of the total power consumption in microprocessors, there is a pressing need to reduce the power requirements of on-chip memory while making sure the data stored in the memory cells remains unchanged. This paper reports design of low leakage Static Random Access Memory (SRAM) Bit-Cell and Array. The SRAM cell and array were designed using 180nm technology and analyzed at 25°C with V DD of 1.8V using Cadence tool. The proposed SRAM cell showed an improvement of around 65% in average SPD over the 6T SRAM cell during the write ‘1’ operation and an improvement of around 66% in average SPD over the 6T SRAM cell during the write ‘0’ operation. Write and Read access times of the proposed 1 kB SRAM Array were recorded to be 27.92% and 25% faster than the 1 kB 6T SRAM Array respectively.