Low-leakage 9-CN-MOSFET SRAM cell with enhanced read and write voltage margins

Yanan Sun,Hailong Jiao,Volkan Kursun

doi:10.1109/icm.2014.7071832

Low-leakage 9-CN-MOSFET SRAM cell with enhanced read and write voltage margins

Yanan Sun, Hailong Jiao + Show 1 more

https://doi.org/10.1109/icm.2014.7071832

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Publication Date: Dec 1, 2014

Citations: 1

Affiliation: Eindhoven University of Technology, Hong Kong University of Science and Technology, University of Hong Kong

#Static Random-access Memory Cell #6T Static Random-access Memory Cell + Show 8 more

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Abstract

A novel static random-access memory (SRAM) cell with nine carbon nanotube MOSFETs (9-CN-MOSFETs) is proposed in this paper. With the new 9-CN-MOSFET SRAM cell, the read data stability is enhanced by 99.09% while providing similar read speed as compared to the conventional six-transistor (6T) SRAM cell in a 16nm carbon nanotube transistor technology. The worst-case write voltage margin is increased by 4.57x with the proposed 9-CN-MOSFET SRAM cell as compared to the conventional 6T SRAM cell. Furthermore, a 1Kibit SRAM array with the new memory cells consumes 34.18% lower leakage power as compared to the memory array with 6T SRAM cells in idle mode.

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