Thermal Through Silicon Via Research Articles

A review of physical heat dissipation methods for 3D integrated technology

Three-dimensional integrated circuits have higher integration than two-dimensional integrated circuits, and can obtain higher performance and lower power consumption in a certain space. In order to fulfill higher efficiency, thermal management becomes particularly important in 3D integration technology. However, the traditional heat dissipation method cannot satisfy the heat dissipation needs of three-dimensional integrated circuits, which require better heat dissipation methods to be developed. This paper introduces the realization of three-dimensional integrated circuit using silicon via (TSV) technology, which allows the chip to be vertically stacked to transmit information. This paper summarizes the research methods and findings of three-dimensional integrated circuit heat dissipation in recent years, including thermal through silicon via (TTSV) and microchannel cooling. It also emphasizes the advantages and disadvantages of both mehods, and the challenges faced in current research via an overview. The future research trend for both heat dissipation methods mainly consists of combining special algorithms to achieve thermal-electrical codesign and thermal management of three-dimensional integrated circuits.

Noise coupling reduction using temperature enhanced device for future integrated circuit integration applications

<p>Information technology-to-internet of things may have succeeded because of fast silicon chip capability expansion. Moore's law, which reduces device size, boosted integrated circuit (IC) performance. Delay rises with highdensity connection parasitic capacitance. Interconnect delays have surpassed transistor delays and slowed progress. An alternative is required now to reduce connection latency. The third dimension is used in popular 3D IC technology IC technology requires through silicon via (TSV) for signal integrity and heat mitigation. Noise coupling hinders electrical communication between signal-carrying TSVs (aggressive TSVs) and ground TSVs (victim TSVs), a 3D IC bottleneck. TSVs must be dielectrically insulated from Si substrates to avoid electrical signal interference. Additionally, first-order modelling will confirm the suggestions. This article proposes using the nanosheet field effect transistor (NSFET) to overcome 3D IC noise coupling and complementary metal oxide semiconductor (CMOS) technology nodes. After discussing the electronic industry and sub nm, several basic metrics and criteria for developing electronic components are presented. The first technique uses Perylene-N's exceptional noise-cancelling characteristics. Second technique uses electrical TSV (ETSV), thermal TSV (TTSV), and heat source models to measure noise coupling on numerous ICs. The third proposes many noise-reducing materials. The suggested structures outperform traditional approaches.</p>

Thermal and mechanical reliability of thermal through-silicon vias in three-dimensional integrated circuits

This research aims to explore the influences of shapes, structures, and arrangements of thermal through-silicon vias (TTSVs) on the thermal and mechanical reliability of a three-dimensional integrated circuit (3D IC). For this purpose, a finite element model coupling the temperature and stress fields in a representative 3D IC with three layers of dies was established to allow numerical simulation of thermal and mechanical reliability caused by the above three factors. The research results show that firstly, rectangular TTSVs have better heat transfer performance than commonly used circular TTSVs of the same area. However, the former is more likely to cause problems pertaining to mechanical reliability in dies. Secondly, compared with the in-line mode of arrangement, the staggered arrangement mode can enable the more compact and uniform arrangement of TTSVs and improve the capacity for heat conduction between adjacent TTSVs, thus reducing the hotspot temperature: meanwhile, the thermal stress rises giving rise to a contradiction between the conventional means of enhancing the heat transfer performance of TTSVs and the resulting increase of thermal stress. Finally, by adding air gaps to TTSVs, the thermal stress around TTSVs can be reduced, while the heat transfer performance also decreases. If air gaps are replaced with carbon nanotubes (CNTs), such a problem can be alleviated. The analysis methods and research results can provide an important reference for the trade-off between thermal reliability and mechanical reliability in 3D ICs in engineering practice.

Distribution optimization of thermal through-silicon via for 3D chip based on thermal-mechanic coupling

This study establishes a unit cell model of thermal-mechanical coupling of 3D chip thermal through-silicon via (TTSV), and conducts optimization study under the constraints of the given ratio of total unit cell volume to TTSV volume. A single-degree-of-freedom optimization study with TTSV spacing as the design variable was first carried out to analyze the impact laws of heat flow density in the hot spot region, TTSV filling material and volume share on the optimal structure and maximum temperature. The results of the two-degree-of-freedom optimization with TTSV spacing and TTSV array rotation angle as design variables were further investigated to determine the distribution of thermal stresses. The maximum temperature of the cell decreases and then increases with the increase in the TTSV pitch, regardless of the rotation angle of the TTSV array, and there exists a minimum value. The higher the temperature, the higher the thermal stress. Thermal stress is always concentrated in the inner and edge regions of the TTSV.

Optimized method for thermal through silicon via placement with non-uniform heat sources in 3-D-IC

In the past few years, thermal through silicon via (TTSV) has been experimentally investigated as an effective heat dissipation path. Although a lot of heat dissipation-related issues have been solved in 3-D integrated circuit (3-D-IC), there are neglections in TTSV placement with non-uniform heat sources so far. In this study, a unique optimization is proposed to locate TTSV while effectively alleviating hot spots in 3-D-IC. The thermal dissipation of non-uniform heat sources are studied using the finite element method. The simulation results show that the minimum temperature is reduced by 2.1% compared with peak temperature in the single-layer chip, and by 1.9% in the three-layer chip.

A universal high-efficiency cooling structure for high-power integrated circuits☆

• A novel micro-channel heat sink(GFSMs MCHS) and an electronic cooling structure(3D-HDS) are designed. • GFSMs MCHS can reduce thermal resistance of regular MCHS by more than 57%. • The thermal resistance of GFSMs MCHS can be reduced to below 0.15 with a pump power of 0.04 W. • 3D-HDS can reduce the thermal resistance and MATD (mean absolute temperature difference) of regular MCHS by more than 40%. Nowadays, the growing number of electronic components in integrated circuit(IC) chips require higher cooling efficiency. Here we propose a universal efficient cooling structure based on Micro-Channel Heat Sink (MCHS), which can be applied to heat dissipation of IC chips with uniform and non-uniform heat fluxes. When using GFSMs (Gradually-Higher Fins Spilt-Flow Microstructures) MCHS to cool an IC chip with a uniform heat flux of 100 W/cm 2 , the thermal resistance and MATD (mean absolute temperature difference) of regular MCHS can be reduced by 57% and 77%. At the same time, the GFSMs MCHS can reduce the thermal resistance to less than 0.28 K/W with only 1/4 of the pressure drop of the regular MCHS, and the thermal resistance can be reduced to below 0.15 K/W with a pump power of 0.04 W. In addition, TTSV (Thermal Through Silicon Via) is combined with a split-flow microstructure to form a three-dimensional heat dissipation structure (3D-HDS). When using 3D-HDS MCHS to cool a chip containing a 1250 W/cm 2 heat flux hotspot, simulations show that the thermal resistance and MATD decreased by more than 40% compared to regular MCHS. The cooling structure will have broad application prospects in the field of high-power integrated circuits and electronic cooling.

Design and implementation of thermal collection networks in 3-D IC structures

The empirical affirmation in the electronics industry is that the power of chips per unit area is growing exponentially. The amount of heat generated is equal to the power; hence as power per unit area increases, so does the amount of heat generated within the chip. Thus, it necessary to mitigate the thermal problems of electronic systems. If not addressed or suppressed, thermal problems can lead to various issues including dielectric breakdown, electromigration, material creeping, unwanted chemical reactions, board warpage, drift in performance, and indirect heating. In this study, a dedicated thermal collection network (TCN) in the back end of the line area of an electronic chip was investigated. This network can help in creating a connection using a thermal through Silicon via (TTSV) to pump up the thermal energy to the heat-sink–fan assembly. Pre-empting heat from the sources could manage the thermal issues arising in chips as well as three-dimensional integrated circuit (3-D IC) structures. The finite-element method was the tool used for analysis. 31.62% of heat suction in TCNs of monolithic ICs, 11.36% in TCNs of 3-D IC structures, and 35.34% of heat suction in junctions of TTSVs compared with different approaches without the postulate used here. This procedure is expected to lead to a new path for redesigning electronic chips and 3-D IC structures.

Effectiveness of thermal redistribution layer in cooling of 3D ICs

AbstractA cooling system composed of a thermal redistribution layer (TRDL) and a thermal through‐silicon via (TTSV) is proposed for three‐dimensional integrated circuits (3D ICs). According to the Fourier heat flow analysis theory, the heat flow model of the proposed cooling system is established and verified by finite element analysis (FEA). It is shown that the maximum error between the heat flow model and FEA is 2.98%, and the maximum temperature of 3D ICs can be reduced by 4.43°C. The established horizontal heat dissipation channel can effectively solve the heat dissipation problem in 3D ICs.

Thermal TSV Optimization and Hierarchical Floorplanning for 3-D Integrated Circuits

While 3-D integrated circuits (ICs) offer many advantages over 2-D ICs, thermal management challenges remain unresolved. Thermal through-silicon-vias (TTSVs) are TSVs that facilitate heat transfer across stacked dies without carrying signal and provide a potential thermal management solution to 3-D ICs. However, the use of TTSVs increases the distance between IC blocks and signal delay. The trade-off between temperature and wirelength is difficult to avoid in TTSV-integrated 3-D ICs. Here, we present a hierarchical approach to optimize the floorplan of a 3-D Nehalem-based multicore processor via simulated annealing (SA). Our simulations show that an increase in the TTSV area accompanies a decrease in peak temperature but the wirelength strongly depends on the TTSV placement, which is uniquely optimized for each case of the allowed TTSV area. Compared to the floorplan with a fixed TTSV placement that places TTSV between cores, our algorithm optimally places TTSVs between IC blocks and finds an optimal floorplan with the minimum cost of peak temperature, wirelength, and area at 6% TTSV area overhead. The peak temperature is reduced from 116 °C to 100 °C with only a 3.5% increase in wirelength. Our floorplan optimization method can provide effective thermal management solutions to 3-D ICs.

Facile approach to mitigate thermal issues in 3D IC integration using effective FIN orientation

Thermal through silicon via (TTSV) and heat spreaders plays a vital role in heat management in 3-Dimentional IC integration. However in recent years FIN to TTSV and heat spreaders has proposed to detects and spread heat in any one direction which leads to the damage of an integration circuit (IC). This paper proposes a FIN with optimal directions and heat spreaders to spread the heat in various directions and finally the heat absorb towards heat sink effectively. In this work, we have also demonstrated various thermal cooling effects and its impact on the distribution of potential across IC at different conditions. We have studied these using FEM Simulator for (1) 3D IC architecture with FIN and heat spreaders using Graphene and CNT material, (2) TTSV with FIN and heat spreaders of Graphene, (3) TTSV with fin and heat spreaders of CNT, (4) TTSV with FIN direction towards heat source made of Graphene and CNT, and (5) TTSV with FIN direction towards TSV made of CNT and Graphene. Our result shows that CNT has better thermal cooling management towards heat source as well TSVs than Graphene with order greater than 100 Kelvin.

Noise performance improvement in 3D IC integration utilizing different dielectric materials

Semiconductor Industries are mainly facing problems by using planar integration (2D IC) in order to overcome the paradigm shift has been adopted as vertical IC integration so called 3D IC. It not only provides higher bandwidth, higher system performance, but also consumes less power with system scaling. 3D IC has an ability to coordinate IC chips by stacking them vertically and electrically associated utilizing TSV's (Through Silicon Via). By utilizing TSV's in 3D IC, TSV noise coupling is one of the vital factors for the system performance aspects. TSV's play major role in carrying the electrical signal between the IC’s of 3D integrated structures. Noise coupling is the major drawback between the signal carrying TSV’s (ETSV) and victim TSV’s. In this work, we have shown better electrical integrity by reducing the noise coupling from TSV to Silicon substrate by essentially changing the CMOS compatible dielectric materials as liner structures. In addition to this performance of various proposed structures are analyzed and verified under different parameters like electrical signal and at high frequencies. Also, the noise coupling analysis has been studied for Electrical TSV’s (ETSV), TTSV (Thermal Through Silicon Via) and heat source. Finally, our work shows liner material Teflon AF1600 shows comparably better noise coupling performance for all the proposed models even at higher frequencies like THz.

Temperature-Aware Floorplanning for Fixed-Outline 3D ICs

Thermal characteristics have been considered as one of the most challenging problems in 3D integrated circuits (3D ICs). The vertically stacked multiple layers of active devices cause a rapid increase of power density and the thermal conductivity of the dielectric layers inserted between device layers for insulation is quite low compared to silicon and metal, which make the peak temperature of 3D ICs rise, leading to the performance degradation. In this paper, instead of inserting Thermal Through Silicon Vias (TTSVs) to reduce the peak temperature, a temperature-aware floorplanning algorithm based on simulated annealing for fixed-outline 3D IC is proposed. The concept of “hot” block is given, by placing the “hot” block of the 3D IC on the bottom layer of the chip (near the radiator) and reasonable intra-layer and inter-layer heat limitation, the peak temperature of the 3D IC is minimized. The number, area and wirelength of the TSVs are also considered in this paper. The results show that the proposed temperature-aware 3D IC floorplanning can effectively reduce the chip peak temperature and the number of TSVs with reasonable area, wirelength and time overhead.

Thermal and Wirelength Optimization With TSV Assignment for 3-D-IC

3-D-IC is an emerging technology that overcomes the drawbacks of 2-D-IC and a vital structure called through-silicon via (TSV) is used to connect the adjacent layers vertically. In this paper, based on graph theories, we formulate the TSV assignment as an integer multicommodity min-cost (IMCMC) problem, and using multilevel algorithm, we get optimal solution. During the assignment, the capacity of the grid could be insufficient to contain the flows so that conditional grid extension effectively relieves the capacity limits and accelerate running speed. Thermal resistive model is introduced to simulate the heat dissipation of chip and estimate temperature distribution each layer. By inserting the thermal TSV, the temperature of superheated region is reduced. Moreover, considering about a more complicated situation, we propose a method to assign multipins in a net. The experimental results demonstrate our model in the IMCMC network using multilevel algorithm achieve optimized congestion, less wirelength, higher running speed, and reduced temperature.

System-Level Analysis of 3D ICs with Thermal TSVs

3D stacking of integrated circuits (ICs) provides significant advantages in saving device footprints, improving power management, and continuing performance enhancement, particularly for many-core systems. However, the stacked structure makes the heat dissipation a challenging issue. While Thermal Through Silicon Via (TTSV) is a promising way of lowering the thermal resistance of dies, past research has either overestimated or underestimated the effects of TTSVs as a consequence of the lack of detailed 3D IC models or system-level simulations. Here, we propose a simulation flow to accurately simulate TTSV effects on 3D ICs. We adopt benchmarks from Splash-2 running on a full-system mode of the gem5 simulator, which generates all the system component activities. McPAT is used to generate the corresponding power consumption and the power traces are fed to HotSpot for thermal simulation. The temperature profiles of 2D and 3D Nehalem-like ×86 processors are compared. TTSVs are later placed close to hotspot regions to facilitate heat dissipation; the peak temperature of 3D Nehalem is reduced by 5--25% with a small area overhead of 6%. By using a detailed 3D thermal model, full-system simulation, and a validated thermal simulator, our results show accurate thermal analysis of 3D ICs.

Thermal management of the hotspots in 3-D integrated circuits

Vertical integration for microelectronics possesses significant challenges due to its fast dissipation of heat generated in multiple device planes. This paper focuses on thermal management of a 3-D integrated circuit, and micro-channel cooling is adopted to deal with the 3-D integrated circuitthermal problems. In addition, thermal through-silicon vias are also used to improve the capacity of heat trans-mission. It is found that combination of microchannel cooling and thermal through-silicon vias can remarkably alleviate the hotspots. The results presented in this paper are expected to aid in the development of thermal design guidelines for 3-D integrated circuits.

End-to-End Analysis of Integration for Thermocouple-Based Sensors Into 3-D ICs

Solutions to the integration challenges of a new thermal sensor technology into 3-D integrated circuits (ICs) will be discussed in this paper. Our proposed architecture uses bimetallic thin-film thermocouples, which are thermally linked to points of measurement throughout the 3-D stack with dedicated vias. These vias will be similar to thermal through-silicon vias (TSVs) in structure, yet different in functionality. We propose a low-overhead design methodology by linking the sensor placement task with the existing thermal TSV planning phase for 3-D ICs. A fraction of thermal TSV resources is decoupled from their original use and repurposed for the temperature sensing infrastructure. Tradeoffs concerning the reduction of the thermal TSV resources are investigated. Furthermore, we present an end-to-end system, including the physical realization of the sensor network as well as its analog interface circuitry with the sensor data sampling unit. We demonstrate the operation and correctness of this interface with transistor-level simulations. Next, through thermal modeling and simulation using a state-of-the-art tool (FloTHERM), we demonstrate that we can achieve high accuracy (1 °C error) in temperature tracking while still maintaining the effectiveness of the thermal TSVs in heat management (conforming to a peak temperature constraint of 95 °C).

Stacking Signal TSV for Thermal Dissipation in Global Routing for 3-D IC

With no further shrinking of device size, 3-D chip stacking by through-silicon-via (TSV) has been identified as an effective way to achieve better performance in speed and power. However, such solution inevitably encounters challenges in thermal dissipation since stacked dies generate a significant amount of heat per unit volume. We leverage an integrated design methodology of stacked-signal-TSVs to minimize temperature. Based on this structure, a three-stage TSV locating algorithm in global routing is designed. We demonstrate that our results, compared with baseline circuits, have 17% temperature reduction with 3% wiring overhead and no performance loss calculated by 3-D Elmore delay model. Compared with the paper by Cong and Zhang where additional thermal TSVs are inserted, our experimental results have in average 23% less TSVs with the same temperature constraint. Compared with the paper by Pathak and Lim, where movable signal TSVs are relocated to reduce temperature in hotspot regions, our result has 8% more temperature reduction with the same number of signal TSVs.

Solving Thermal Issues in a Three-Dimensional-Stacked-Quad-Core Processor by Microprocessor Floor Planning, Microchannel Cooling, and Insertion of Through-Silicon-Vias

The electronics industry is heading toward the three-dimensional (3D) microprocessor to cope with higher computing workloads. The 3D stacking of the processor and the memory components reduces the communication delay in multicore system-on-a-chip (SoCs), owing to reduced system size and shorter interconnects. The shorter interconnects in a multicore system lowers the memory access latencies and contributes to improvements in memory access bandwidth. The shorter interconnects in stacked architectures also enables small drivers for interconnections which further reduce interconnection-level-energy dissipations. On the down side, the 3D-stacked architectures have high thermal resistance, which in conjunction with poor thermal management techniques, poses a thermal threat to the reliability of the device. This paper establishes the significance of the microprocessor floor planning and single-phase microchannel cooling for solving the thermal issues arising in the 3D-stacked-quad-core processor. The 3D-stacked-quad-core processor considered in this study comprises of symmetric nonuniformly powered quad-core processor, liquid-cooled microchannel heat sink, dynamic random access memory (DRAM), thermal interface material (TIM), and heat spreader. The electrical through-silicon-vias (TSVs) between the processor and DRAM serve as interconnects, while the thermal TSVs reduce the internal thermal resistance. The effective cooling of the 3D-stacked-quad-core processor depends on the TSVs, quad-core layout and the optimized design of the microchannel heat sink for the desired coolant. The microchannel cooling of the 3D-stacked processor is done both by planar flow and impingement flow. The thermal efficiency of the cooling techniques is evaluated on the basis of hot spot temperature, hot spot spread, and number of hot spots.

Long Length, High-Density Carbon Nanotube Film Grown by Slope Control of Temperature Profile for Applications in Heat Dissipation

We have developed a new growth method for a film of dense, vertically aligned carbon nanotubes (CNTs). We varied the slope of the growth temperature profile between 450 and 800 °C. By using the method with an Fe/Ti catalyst, the filling factor of the CNT film was measured to be 0.28, which is 20 times denser than that in the case where conventional CVD growth is utilized. We name this growth method the slope control of temperature profile (STEP) growth. Another feature of CNT films obtained by STEP growth is their mirror like surfaces. This allows for the measurement of the thermal conductivity by a pulse optical heating thermoreflectance method. The maximum thermal conductivity of the STEP-grown CNT film was 260 W m-1 K-1, which is higher than those of a solder and Si. This result suggests that STEP-grown CNT films are effective heat dissipation materials and can be used as thermal interface material (TIM) and thermal through silicon via (TSV).

Co‐design of micro‐fluidic heat sink and thermal through‐silicon‐vias for cooling of three‐dimensional integrated circuit

Three-dimensional integrated circuits (3D-ICs) bring about new challenges to chip thermal management because of their high heat densities. Micro-channel-based liquid cooling and thermal through-silicon-vias (TSVs) have been adopted to alleviate the thermal issues in 3D-ICs. Thermal TSV enables higher interlayer thermal conductivity thereby achieving a more uniform thermal profile. Although somewhat effective in reducing temperatures, they are limited by the nature of the heat sink. On the other hand, micro-channel-based liquid cooling is significantly capable of addressing 3D-IC cooling needs, but consumes a lot of extra power for pumping coolant through channels. This study proposes a hybrid 3D-IC cooling scheme which combines micro-channel liquid cooling and thermal TSV with one acting as heat removal agent, whereas the other enabling beneficial heat conduction paths to the micro-channel structures. The experimental results show that the proposed hybrid cooling scheme provides much better cooling capability than using only thermal TSVs, although consuming 56% less cooling power compared with pure micro-channel cooling.