Temperature-Aware Floorplanning for Fixed-Outline 3D ICs

Tianming Ni,Hao Chang,Lin Lu,Xueyun Li,Qi Xu,Shidong Zhu,Huaguo Liang,Zhengfeng Huang

doi:10.1109/access.2019.2942839

Abstract

Thermal characteristics have been considered as one of the most challenging problems in 3D integrated circuits (3D ICs). The vertically stacked multiple layers of active devices cause a rapid increase of power density and the thermal conductivity of the dielectric layers inserted between device layers for insulation is quite low compared to silicon and metal, which make the peak temperature of 3D ICs rise, leading to the performance degradation. In this paper, instead of inserting Thermal Through Silicon Vias (TTSVs) to reduce the peak temperature, a temperature-aware floorplanning algorithm based on simulated annealing for fixed-outline 3D IC is proposed. The concept of “hot” block is given, by placing the “hot” block of the 3D IC on the bottom layer of the chip (near the radiator) and reasonable intra-layer and inter-layer heat limitation, the peak temperature of the 3D IC is minimized. The number, area and wirelength of the TSVs are also considered in this paper. The results show that the proposed temperature-aware 3D IC floorplanning can effectively reduce the chip peak temperature and the number of TSVs with reasonable area, wirelength and time overhead.

Highlights

Three-dimensional integrated circuits (3D ICs) that employ the through-silicon vias (TSVs) vertically stacking multiple dies provide many benefits, such as high density, high bandwidth, and low power [1]–[6]
Instead of inserting Thermal Through Silicon Vias (TTSVs) to reduce the peak temperature, a temperature-aware floorplanning algorithm based on simulated annealing for fixed-outline 3D integrated circuits (3D ICs) is proposed
The results show that the proposed temperatureaware 3D IC floorplanning can effectively reduce the chip peak temperature and the number of TSVs with reasonable area, wirelength and time overhead

Summary

INTRODUCTION

Three-dimensional integrated circuits (3D ICs) that employ the through-silicon vias (TSVs) vertically stacking multiple dies provide many benefits, such as high density, high bandwidth, and low power [1]–[6]. Layers inserted between device layers for insulation is quite low compared to silicon and metal [8], [9], which make the peak temperature of 3D ICs rise, leading to the performance degradation. It is very important to consider the number and peak temperature of TSV during floorplanning for designing 3D ICs with superior performance. Wong and Sung Kyu [11] presented a heat sink TTSV insertion algorithm during 3D floorplanning, which effectively reduced the peak temperature of the chip by using the least number of heat sinks. Instead of inserting TTSVs to reduce the peak temperature, a temperature-aware floorplanning algorithm based on simulated annealing for fixed-outline 3D IC is proposed. The results show that the proposed temperatureaware 3D IC floorplanning can effectively reduce the chip peak temperature and the number of TSVs with reasonable area, wirelength and time overhead. The B∗ tree can be transformed into a one-to-one floorplanning

TEMPERATURE ESTIMATION

INTRA-LAYER AND INTER-LAYER THERMAL

CONCLUSION