Noise performance improvement in 3D IC integration utilizing different dielectric materials

Abstract

Semiconductor Industries are mainly facing problems by using planar integration (2D IC) in order to overcome the paradigm shift has been adopted as vertical IC integration so called 3D IC. It not only provides higher bandwidth, higher system performance, but also consumes less power with system scaling. 3D IC has an ability to coordinate IC chips by stacking them vertically and electrically associated utilizing TSV's (Through Silicon Via). By utilizing TSV's in 3D IC, TSV noise coupling is one of the vital factors for the system performance aspects. TSV's play major role in carrying the electrical signal between the IC’s of 3D integrated structures. Noise coupling is the major drawback between the signal carrying TSV’s (ETSV) and victim TSV’s. In this work, we have shown better electrical integrity by reducing the noise coupling from TSV to Silicon substrate by essentially changing the CMOS compatible dielectric materials as liner structures. In addition to this performance of various proposed structures are analyzed and verified under different parameters like electrical signal and at high frequencies. Also, the noise coupling analysis has been studied for Electrical TSV’s (ETSV), TTSV (Thermal Through Silicon Via) and heat source. Finally, our work shows liner material Teflon AF1600 shows comparably better noise coupling performance for all the proposed models even at higher frequencies like THz.