Abstract
The empirical affirmation in the electronics industry is that the power of chips per unit area is growing exponentially. The amount of heat generated is equal to the power; hence as power per unit area increases, so does the amount of heat generated within the chip. Thus, it necessary to mitigate the thermal problems of electronic systems. If not addressed or suppressed, thermal problems can lead to various issues including dielectric breakdown, electromigration, material creeping, unwanted chemical reactions, board warpage, drift in performance, and indirect heating. In this study, a dedicated thermal collection network (TCN) in the back end of the line area of an electronic chip was investigated. This network can help in creating a connection using a thermal through Silicon via (TTSV) to pump up the thermal energy to the heat-sink–fan assembly. Pre-empting heat from the sources could manage the thermal issues arising in chips as well as three-dimensional integrated circuit (3-D IC) structures. The finite-element method was the tool used for analysis. 31.62% of heat suction in TCNs of monolithic ICs, 11.36% in TCNs of 3-D IC structures, and 35.34% of heat suction in junctions of TTSVs compared with different approaches without the postulate used here. This procedure is expected to lead to a new path for redesigning electronic chips and 3-D IC structures.
Highlights
When a chip is designed to meet the static current–resistance (IR) drop, typical power grid and power switches are added
A thermal collection network (TCN) can be connected to the ground so that the thermal through Silicon via (TTSV) can be connected to ground paths of current to alleviate the capacitance of the metals
For the design of a thermal grid associated with a collective network, a model has been proposed along with the necessary information about physical attributes that can be subsequently used in designing optimal thermal collection/reception networks for an “n” metal layer system
Summary
When a chip is designed to meet the static current–resistance (IR) drop, typical power grid and power switches are added. Based on the logic switching operation for a specific period, a hotspot could form because of the massive dynamic current drawn by localized logic areas These hotspots can be fixed through decap cells while constraining them to a particular percentage of targeted voltages. It has been shown that these hotspots are important attributes in the process of thermal energy accumulation They help in distributing thermal energy to the integrated wires and substrates of the chip by inducing indirect heat to the chip logic as well as other components. In such a situation, the IR drop targeted by the decap cells improvises on the advanced nodes, and it would be minimal
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