Thermal TSV Optimization and Hierarchical Floorplanning for 3-D Integrated Circuits

Abstract

While 3-D integrated circuits (ICs) offer many advantages over 2-D ICs, thermal management challenges remain unresolved. Thermal through-silicon-vias (TTSVs) are TSVs that facilitate heat transfer across stacked dies without carrying signal and provide a potential thermal management solution to 3-D ICs. However, the use of TTSVs increases the distance between IC blocks and signal delay. The trade-off between temperature and wirelength is difficult to avoid in TTSV-integrated 3-D ICs. Here, we present a hierarchical approach to optimize the floorplan of a 3-D Nehalem-based multicore processor via simulated annealing (SA). Our simulations show that an increase in the TTSV area accompanies a decrease in peak temperature but the wirelength strongly depends on the TTSV placement, which is uniquely optimized for each case of the allowed TTSV area. Compared to the floorplan with a fixed TTSV placement that places TTSV between cores, our algorithm optimally places TTSVs between IC blocks and finds an optimal floorplan with the minimum cost of peak temperature, wirelength, and area at 6% TTSV area overhead. The peak temperature is reduced from 116 °C to 100 °C with only a 3.5% increase in wirelength. Our floorplan optimization method can provide effective thermal management solutions to 3-D ICs.