T-gate Process Research Articles

Fabrication of AlGaN/GaN Fin-Type HEMT Using a Novel T-Gate Process for Improved Radio-Frequency Performance

To increase the radio-frequency (RF) performance of AlGaN/GaN-based fin-type high electron mobility transistors (HEMTs), a novel T-gate process was developed and applied to fabricate a device with high RF performance. In a single lithography process, the applied T-gate process shows a technique for forming a T-gate using the reactivity difference of several photoresists. The fabricated device has a steep fin width (W <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">fin</sub> ) of 130 nm, a fin height (H <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">fin</sub> ) of 250 nm, and a gate length (L <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">G</sub> ) of 190 nm. The device exhibits a low leakage current (I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">off</sub> ) of 6.6 × 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-10</sup> A/mm and a high I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">on</sub> /I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">off</sub> current ratio of 4.7 × 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">8</sup> . Moreover, the fabricated device achieved a high cut-off frequency (f <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">T</sub> ) of 9.7 GHz and a very high maximum oscillation frequency (f <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">max</sub> ) of 27.8 GHz. The f <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">max</sub> value of the proposed device is 138% higher than that of GaN-based fin-type HEMTs without T-gate.

ScAlN/GaN High-Electron-Mobility Transistors With 2.4-A/mm Current Density and 0.67-S/mm Transconductance

We report the dc and RF performance of ScAlN/GaN high-electron-mobility transistors (HEMTs). The ScAlN/GaN material was epitaxially grown onto a GaN template on a 4-in 4H-SiC substrate by molecular beam epitaxy. The sheet resistance was measured to be 236 ± 4 $\Omega /\square $ across the wafer by the transfer length measurement. Selective area regrowth of highly doped GaN was implemented to reduce contact resistance ( ${R}_{C}$ ) as low as 0.1 $\Omega \cdot \textsf {mm}$ . HEMT devices with $\textsf {2}\times \textsf {150}\,\,\mu \text{m}$ gate width and 140-nm T-gate process show a maximum current density and a transconductance of 2.4 A/mm and 0.67 S/mm, respectively. The extrinsic small-signal gain was measured as a function of drain bias and gate length with extrinsic cutoff frequency and maximum oscillation frequency reported up to 88 and 91 GHz, respectively.

A simple silicon compatible 40 nm electroplated copper T-gate process

This paper reports a simple route to fabricating T-gate like structures with footprint of 40nm using a copper electroplating process and a single electron beam lithography step without the need for lift-off. To our knowledge, these are the smallest such structures demonstrated using this approach which could also be implemented straightforwardly using conventional stepper or nanoimprint lithography for low cost, high volume silicon compatible manufacture.

Thermally reflowed ZEP 520A for gate length reduction and profile rounding in T-gate fabrication

The characteristics of thermally reflowed ZEP 520A-7 (ZEP), a resist commonly used in electron beam lithography, are presented for use as a gate stem resist layer in T-gate process development. As-developed ZEP lines possess a resist sidewall profile that displays varying amounts of undercut, which are determined by the conditions used to expose the line. The authors find that after thermal reflow, the top of the ZEP profile becomes substantially rounded in shape, mitigating “metal cathedraling” problems, a yield-affecting issue that becomes more pronounced as the gate length is reduced. In addition to profile rounding, a linewidth reduction of over 100 nm is observed, and this process has been used to produce gate lengths in the 30–40 nm range. The changes in feature size and the final profile shape depend on the as-developed sidewall angle. Additionally, the ZEP reflow process saturates after a certain amount of time, so reproducibility is not hindered by a lack of precise control in timing. As larger lines can be used to produce smaller features via reflow, the potential for faster throughput exists due to the use of a higher beam current, which would normally limit the attainable minimum feature size.

GaN on Si HEMT with 65% power added efficiency at 10 GHz

A 65% power added efficiency (PAE) at 10 GHz for a AlGaN/GaN high electron mobility transistor on silicon substrate is presented. This PAE is achieved with an associated output power of 6.1 W/mm and an associated gain of 13.1 dB for a 400 µm gate-width transistor biased at 40 V drain voltage. Epitaxial AlGaN/GaN layers are grown on 4-inch silicon substrate. Nitride defined 0.25 µm T-gate process, which allows formation of an integrated field plate, is used for these devices. A source-connected second field plate is also implemented to improve device performance at high operation voltage.

Asymmetrically Recessed 50-nm Gate-Length Metamorphic High Electron-Mobility Transistor With Enhanced Gain Performance

We report the design, fabrication and characterization of ultrahigh gain metamorphic high electron-mobility transistors. In this letter, a high-yield 50-nm T-gate process was successfully developed and applied to epitaxial layers containing high indium mole fraction InGaAs channels grown on GaAs substrates. A unique gate recess process was adopted to significantly increase device gain by effectively suppressing output conductance and feedback capacitance. Coupled with extremely small 10 mum times 25 mum via holes on substrates thinned to 1 mil, we achieved a 13.5 dB maximum stable gain (MSG) at 110 GHz for a 30-mum gate-width device. To our knowledge, this is the highest gain performance reported for microwave high electron-mobility transistor devices of similar gate periphery at this frequency, and equivalent circuit modeling indicates that this device will operate at frequencies beyond 300 GHz.

50 nm In 0.8 GaP/In 0.4 AlAs/In 0.35 GaAs metamorphic HEMTs with ZEP/UV5 bilayer T-gate

By using a novel bilayer resist process, 50 nm In 0.8 GaP/In 0.4 AlAs/In 0.35 GaAs metamorphic HEMTs on GaAs substrate have been successfully fabricated with high yield and uniformity. This process has an advantage over the conventional T-gate process. After definition of the bottom layer, the top layer is exposed, which prevents widening of the bottom layer. The devices with a novel bilayer T-gate exhibited excellent characteristics such as a maximum extrinsic transconductance (g mldrmax ) of 800 mS/mm, an on-state breakdown voltage (BV on ) of 3 V, a current-gain-cutoff frequency (f T ) of 254 GHz, and a maximum oscillation frequency (f max ) of 360 GHz in spite of low indium content of 35% in the channel.

Imprint lithography issues in the fabrication of high electron mobility transistors

In earlier work we described procedures for the fabrication of High Electron Mobility Transistors (HEMTs) using nanoimprint lithography to produce T-shaped resist profiles for gate metallization. For reliable liftoff the T-gate process requires a clear undercut in resist, and this is intrinsically impossible with imprint lithography. In addition, the imprinting process resulted in fracture defects in the resist unless release was carried out at elevated temperatures. Both these problems required improvement. In this article we describe an improved method for obtaining metallized imprinted T-gates by creating resist undercut using a double angled evaporation. HEMTs with self-aligned gate structures were fabricated using this procedure. Multilayer resist stacks were used to investigate resist flow during imprinting and we show that such stacks are not suitable for liftoff enhancement of T-gates. We further show how resist fracture defects can be minimized by increasing the pattern density on the die.

A novel double-recessed 0.2-μm T-gate process for heterostructure InGaP-InGaAs doped-channel FET fabrication

A double-recessed T-gate process has been successfully developed to fabricate 0.2-/spl mu/m gate-length heterostructure InGaP-InGaAs doped-channel FETs (DCFETs) to increase the gate-to-drain breakdown voltage. This technology uses direct electron-beam lithography with a single exposure of a four-layer stack polymethylmethacrylate and polydimethylmethacrylate (photoresists). After the combination of chemical and dry etchings, the double gate-recessed DCFETs exhibit improved DC and RF power performance, as compared with the conventional ones, resulting from the gate-leakage current. The Schottky gate breakdown voltage enhances from 5 to 7 V, and the output power increases from 148 to 288 mW/mm at 5.2 GHz.

High electron mobility transistors fabricated by nanoimprint lithography

High frequency low noise III–V transistors commonly have T-shaped gates since they provide a combination of short gate length and low gate resistance. This paper describes the fabrication of working pHEMT transistors with 120-nm T-shaped gates using a bi-layer nanoimprint lithography process. The main thrust of the work has been to develop a nanoimprinted T-gate process for the fabrication of pHEMTs. The fabrication of silicon stamping tools plays a vital part in transistor fabrication by this technique and the bi-layer enables removal of the residual resist without dry etch damage to the substrate. The paper describes the measures taken to achieve reliable uniform pattern transfer by nanoimprint lithography and the subsequent post imprint fabrication steps used to realise working transistors. The results of device characterisation are presented.

High-performance fully-depleted SOI RF CMOS

A T-gate structure has been implemented in the fabrication of fully depleted silicon-on-insulator MOSFETs. The T-gate process is fully compatible with the standard CMOS and the resulting reduction of gate-resistance significantly improved the RF performance. Measured f <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">max</sub> is 76 GHz and 63 GHz for n- and p-MOSFET with 0.2-μm gate length, respectively. At 2 GHz, a minimum noise figure of 0.4 dB was measured on an n-MOSFET with the T-gate structure.

Novel dual-gate HEMT utilising multiple split gates

We apply the split-gate structure to dual-gate HEMTs, configured so that a parallel array of channels is defined by split gates that control the effective device width whilst a further continuous gate controls the carrier density within the channels defined by the array. This is a different principle of operation to conventional dual-gate HEMTs. We describe the fabrication of the multiple split gates using a modified T-gate process and present device characteristics.

“Safe” solvent resist process for sub-quarter micron T-gates

With the advent of the “green” revolution, the semiconductor industry must develop alternative processes that utilize environmentally friendly products. As a first step toward this end we have demonstrated an electron beam patterned sub-quarter micron T-gate process using safe resists manufactured by Microlithography Chemical Corp. (MCC). Instead of the more conventional chlorobenzene based poly methyl methacrylate (PMMA) and 2-ethoxyethanol copolymer solutions, new anisole based PMMA and an ethyl lactate based copolymer are used. In addition to replacing the non-environmentally friendly resists, we sought to increase gate yield by improving the shape of the resist profile. Focused ion beam (FIB) cross-sectional analysis of 0.2 μm T-gates fabricated using our conventional process showed metal discontinuity at the stem-to-cap transition. This was attributed to a sharp transition in the resist from the bottom layer of PMMA to the copolymer. With the safe resists we sought to grade the transition between the stem and cap to improve metal continuity. Multiple techniques were used to evaluate and characterize the safe resist process. FIB cross sectioning provided a rapid and less destructive method for resist profile inspection. In addition, metal deposition was examined prior to liftoff to view evaporation buildup. Scanning electron microscopy and atomic force microscopy were used to give comparative measures of gate length. A safe resist process for sub-quarter micron T-gate fabrication is described.

Single step lithography for double-recessed gate pseudomorphic high electron mobility transistors

An asymmetric double-recessed gate process achieved through a single lithography step and a combination of wet and dry etching techniques is presented. The double-recessed gate process is beneficial in the fabrication of InGaAs/AlGaAs/GaAs pseudomorphic high electron mobility transistors (PHEMTs) because breakdown voltage is enhanced while surface effects on the drain side of the gate are minimized. In contrast to conventional processes that require two lithography steps, the current process requires only a single lithography step for the asymmetric placement of a T-gate in a wide recess trench. The process utilizes a four-layer resist of polymethylmethacrylate (PMMA) and P(MMA-MAA) exposed by electron beam lithography. Upon development of the resist, a wet selective etch (citric acid:H2O2) is used to define the wide recess trench and then a dry selective etch (SiCl4/SiF4) is used to recess a narrow trench (within the wide recess trench) in which the gate foot rests. This technique can achieve gate lengths of 0.15μm and drain-side wide recess dimensions from 0.15 to 0.55μm while the source-side recess width is kept at or below 0.15 μm. Device results show improved breakdown voltages and output conductance with only slight reduction in transconductance and drain current for the PHEMTs fabricated using the technique as compared to PHEMTs fabricated using a trilayer T-gate process.

Fabrication and dc, microwave characteristics of submicron Schottky-collector AlAs/In0.53Ga0.47As/InP resonant tunneling diodes

We report the fabrication and dc, microwave characteristics of 0.1 μm, Schottky-collector resonant tunnel diodes (SRTDs) in the AlAs/In0.53Ga0.47As/InP material system. Devices with contact areas as small as 0.05 μm2 have been fabricated using electron beam lithography with an interrupted footprint T-gate process. SRTD’s fabricated with 1.4 nm AlAs barriers exhibited a 5×105 A/cm2 peak current density at 0.95 V and a −19 mS/μm2 peak negative conductance. The devices incorporate fully depleted P-doped cap layers to suppress surface leakage currents. From the measured dc and microwave characteristics, a maximum frequency of oscillation fmax=2.2 THz is estimated.

MOCVD-grown InAlAs/InGaAs HEMTs with f T = 200 GHz

The performance of 0.15 mu m gate InAlAs/InGaAs HEMTs grown by MOCVD is reported. The HEMT layer structure exhibited excellent transport properties, indicating the high quality of the heterointerface. The devices fabricated using a T-gate process showed an f/sub T/ of 200 GHz and f/sub max/ of 230 GHz extrapolated from 26 GHz at -6dB/octave. These are the best speed performances of any MOCVD-grown FETs. The results clearly demonstrate that MOCVD is a powerful growth technique for materials for high-speed applications.

A dielectric-defined process for the formation of T-gate field-effect transistors

A novel process for the fabrication of tee- or gamma-shaped gate structures is presented. This process was utilized to fabricate 0.25 mu m*60 mu m and 0.25 mu m*150 mu m T-gate MESFETs. From S-parameter data up to 40 GHz, extrapolated cutoff frequencies as high as 55-65 GHz were obtained. DC yields as high as 80% over 3-in wafers were obtained using this dielectric defined T-gate (DDTG) process. Step-stress measurements indicate device reliability comparable to the normal MESFET process. Relative to multilayer resist processing techniques usually used to form T-gates, it is believed that the DDTG process will substantially increase the yield, uniformity, and reliability of FET-like devices/circuits using T-gates with geometries at or below 0.25 mu m.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Novel T-gate fabrication and high frequency performance for 0.1μm-gate InAlAs/InGaAs HEMT

Cutoff frequencies are measured for sub-0.25 μm-gate InAlAs/InGaAs/InP HEMTs fabricated with a novel T-gate process using ion-beam etching in conjunction with both electron-beam lithography and photolithography. The cutoff frequency of 200GHz is demonstrated by 0.12 μm-gate HEMT.