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Abstract
High frequency low noise III–V transistors commonly have T-shaped gates since they provide a combination of short gate length and low gate resistance. This paper describes the fabrication of working pHEMT transistors with 120-nm T-shaped gates using a bi-layer nanoimprint lithography process. The main thrust of the work has been to develop a nanoimprinted T-gate process for the fabrication of pHEMTs. The fabrication of silicon stamping tools plays a vital part in transistor fabrication by this technique and the bi-layer enables removal of the residual resist without dry etch damage to the substrate. The paper describes the measures taken to achieve reliable uniform pattern transfer by nanoimprint lithography and the subsequent post imprint fabrication steps used to realise working transistors. The results of device characterisation are presented.
Published Version
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