A novel double-recessed 0.2-μm T-gate process for heterostructure InGaP-InGaAs doped-channel FET fabrication

Abstract

A double-recessed T-gate process has been successfully developed to fabricate 0.2-/spl mu/m gate-length heterostructure InGaP-InGaAs doped-channel FETs (DCFETs) to increase the gate-to-drain breakdown voltage. This technology uses direct electron-beam lithography with a single exposure of a four-layer stack polymethylmethacrylate and polydimethylmethacrylate (photoresists). After the combination of chemical and dry etchings, the double gate-recessed DCFETs exhibit improved DC and RF power performance, as compared with the conventional ones, resulting from the gate-leakage current. The Schottky gate breakdown voltage enhances from 5 to 7 V, and the output power increases from 148 to 288 mW/mm at 5.2 GHz.