Static Random Access Memory Devices Research Articles

Study on Single Event Upsets in a 28 nm Technology Static Random Access Memory Device Based on Micro-Beam Irradiation

As an important spaceborne electronic device, the static random access memory (SRAM) device is inevitably affected by the radiation of high-energy particles in space during its space mission. To reveal the single event effect (SEE) mechanism of 28 nm technology SRAM caused by high-energy particles, the sensitive area positioning of single event upsets (SEUs) and the distribution characteristics of multi-cell upsets (MCUs) were studied based on the pinhole heavy ion micro-beam facility. The results show that the actual range of SEUs caused by micro-beam irradiation is 4.8 μm × 7.8 μm. By moving the device platform in small steps (1 μm each step), a one-dimensional positioning method for locating the sensitive area of SEUs was established, which can reduce the dependence of localization accuracy on beam spot size, and the positioning accuracy can be improved to 1 μm. The MCU test indicates that the upset pattern is closely related to the spacing of sensitive areas within adjacent SRAM cells, and the probability of MCUs is reduced by well contacts and bit interleaving.

Effects of Total Ionizing Dose on SRAM Physical Unclonable Functions

The effects of total ionizing dose (TID) on static random access memory (SRAM) physical unclonable functions (PUFs) are studied through X-ray and proton irradiation of commercially available SRAM. Negative shifts in the fractional Hamming weight (FHW) were measured with increasing TID, indicating a migration of bistable cells toward logic low. Additionally, positive shifts in the intra-die fractional Hamming distance (FHD) were measured and indicate changes to the virtual fingerprint of an SRAM PUF with TID, especially in devices that were dosed while holding data. Shifts in inter-die FHD were negligible, allowing individual SRAMs still to be easily identified based on the FHD between a known and unknown sample even after moderate amounts of TID. In some cases, SRAMs could still be identified by their PUFs after the devices had failed. In all cases, the irradiated SRAM devices retained their virtual fingerprint after recovery through annealing.

DEVELOPING A TOOL FOR LOW-POWER MEMORY CELL DESIGN

Memory devices are an important part of integrated circuits. If previously the storage capacity of memory devices did not exceed a few tens of kilobytes, now it reaches terabytes. Due to this, the design of memory devices has become more complicated both technically and temporally. Particularly improvement of the power consumption and aging parameters of memory devices has become difficult. One of the most important problems in modern integrated circuits is the reduction of power consumption. Approximately 80% of the total integrated circuit area is occupied by memory devices, they account for more than 60…70% of the total energy consumption. In static random-access memory devices, the sense amplifiers are the ones with the most power consumption. In the process of reading, they account for about 40% of the total power consumption. The design time is also a major issue in the memory device production. That's why memory devices are designed automatically using existing special libraries. And the elements in the memory devices are designed manually, which affects their design time and cost. This article proposes a software tool that allows to reduce the power consumption of sense amplifiers programmatically. In addition, it allows to effectively study the preselected parameters of the amplifiers.

Comparison of neutron induced single event upsets in 14 nm FinFET and 65 nm planar static random access memory devices

<sec> Based on the wide-spectrum neutron beam (covering thermal neutrons and <i>E</i> > 10 MeV neutrons, with maximum energy of 1.6 GeV) provided by the China Spallation Neutron Source (CSNS), this paper focuses on the single event effect study of 14 nm FinFET large-capacity SRAM and 65 nm planar process SRAM device, using combined techniques of irradiation experiment, reverse analysis, and Monte-Carlo neutron transport simulation. The aim is to reveal the effect of integrated circuit process changing on the sensitivity of neutron induced single-bit and multiple-bit upsets (MBU), and to analyze the inner mechanisms, including the distribution of secondary particles in the sensitive volume, the characteristics of deposited charges, etc. </sec><sec> The results show that compared with the 65 nm device, single event upset (SEU) cross section of the 14 nm FinFET device, induced by <i>E</i> > 10 MeV neutrons, is reduced by about 40 times, while the MBU ratio increases from 2.2% to 7.6%, which is due to the reduction of sensitive volume size of the 14 nm FinFET device (80 nm × 30 nm × 45 nm), pitch, and critical charge (0.05 fC). The main forms of MBU are double-bit upset, triple-bit upset and quadruple-bit upset. Unlike the phenomenon that the 65 nm device is immune to thermal neutrons, the use of the <sup>10</sup>B element near M0 in the 14 nm FinFET device causes it to present the thermal neutron sensitivity to a certain extent. The SEU cross section induced by thermal neutrons is about 4.8 times smaller than that induced by <i>E</i> > 10 MeV neutrons. </sec><sec> Based on the device cross-section and memory area images obtained from the reverse analysis, a device model is established and neutron transport simulation based on Geant4 toolkit is carried out. The <i>E</i> > 10 MeV neutrons result in abundant secondary particle distribution in the sensitive volume of the device, covering n, p into even W. The neutron energy and presence or absence of the W plug near the sensitive volume have an importantinfluence on the type and probability of secondary particles in the sensitive volume. The analysis and calculations show that a large number of high-<i>Z</i> secondary particles with long range and large LET values generated by high-energy neutrons in the sensitive volume of the device are the inducement of MBU, and SEUs mainly result from the contribution of light ions such as p, He, and Si. </sec>

Single event upset on static random access memory devices due to spallation, reactor, and monoenergetic neutrons**Project supported by the National Natural Science Foundation of China (Grant Nos. 11690040 and 11690043) and the Foundation of State Key Laboratory of China (Grant Nos. SKLIPR1801Z and 6142802180304).

This paper presents new neutron-induced single event upset (SEU) data on the SRAM devices with the technology nodes from 40 nm to 500 nm due to spallation, reactor, and monoenergetic neutrons. The SEU effect is investigated as a function of incident neutron energy spectrum, technology node, byte pattern and neutron fluence rate. The experimental data show that the SEU effect mainly depends on the incident neutron spectrum and the technology node, and the SEU sensitivity induced by low-energy neutrons significantly increases with the technology downscaling. Monte–Carlo simulations of nuclear interactions with device architecture are utilized for comparing with the experimental results. This simulation approach allows us to investigate the key parameters of the SEU sensitivity, which are determined by the technology node and supply voltage. The simulation shows that the high-energy neutrons have more nuclear reaction channels to generate more secondary particles which lead to the significant enhancement of the SEU cross-sections, and thus revealing the physical mechanism for SEU sensitivity to the incident neutron spectrum.

Mechanisms of atmospheric neutron-induced single event upsets in nanometric SOI and bulk SRAM devices based on experiment-verified simulation tool**Project supported by the National Natural Science Foundation of China (Grant No. 11505033), the Science and Technology Research Project of Guangdong Province, China (Grant Nos. 2015B090901048 and 2017B090901068), and the Science and Technology Plan Project of Guangzhou, China (Grant No. 201707010186).

In this paper, a simulation tool named the neutron-induced single event effect predictive platform (NSEEP2) is proposed to reveal the mechanism of atmospheric neutron-induced single event effect (SEE) in an electronic device, based on heavy-ion data and Monte-Carlo neutron transport simulation. The detailed metallization architecture and sensitive volume topology of a nanometric static random access memory (SRAM) device can be considered to calculate the real-time soft error rate (RTSER) in the applied environment accurately. The validity of this tool is verified by real-time experimental results. In addition, based on the NSEEP2, RTSERs of 90 nm–32 nm silicon on insulator (SOI) and bulk SRAM device under various ambient conditions are predicted and analyzed to evaluate the neutron SEE sensitivity and reveal the underlying mechanism. It is found that as the feature size shrinks, the change trends of neutron SEE sensitivity of bulk and SOI technologies are opposite, which can be attributed to the different MBU performances. The RTSER of bulk technology is always 2.8–64 times higher than that of SOI technology, depending on the technology node, solar activity, and flight height.

Array Termination Impacts in Advanced SRAM

An essential goal of the static random access memory (SRAM) array termination design is to both terminate as well as maintain a homogeneous environment for the active edge cells in the array. Local layout effects (LLEs) in the array termination design can exert influence on the active array SRAM devices in close proximity to the termination region, which can lead to undesirable inhomogenuities in the array. The impact of LLEs, originating from the array termination design, on SRAM read performance and $V_{\min }$ fail count, are examined using a 14-nm FinFET technology. Large-scale SRAM read performance statistics are analyzed to identify elevated read currents and low-voltage fail counts associated with the array termination. The root cause and modulating factors are explored, and potential solution paths are discussed.

Comparison between Pt/TiO2/Pt and Pt/TaOX/TaOY/Pt based bipolar resistive switching devices

Nonvolatile memories have emerged in recent years and have become a leading candidate towards replacing dynamic and static random-access memory devices. In this article, the performances of TiO2 and TaO2 nonvolatile memristive devices were compared and the factors that make TaO2 memristive devices better than TiO2 memristive devices were studied. TaO2 memristive devices have shown better endurance performances (108 times more switching cycles) and faster switching speed (5 times) than TiO2 memristive devices. Electroforming of TaO2 memristive devices requires ∼4.5 times less energy than TiO2 memristive devices of a similar size. The retention period of TaO2 memristive devices is expected to exceed 10 years with sufficient experimental evidence. In addition to comparing device performances, this article also explains the differences in physical device structure, switching mechanism, and resistance switching performances of TiO2 and TaO2 memristive devices. This article summarizes the reasons that give TaO2 memristive devices the advantage over TiO2 memristive devices, in terms of electroformation, switching speed, and endurance.

A Parallel-Access Mapping Method for the Data Exchange Buffers Around DCT/IDCT in HEVC Encoders Based on Single-Port SRAMs

In the High Efficiency Video Coding (HEVC) standard, a notation of the transform unit (TU) is introduced with four different sizes, i.e., 4 $\times$ 4, 8 $\times$ 8, 16 $\times$ 16, and 32 $\times$ 32, which results in at least two problems in the use of discrete cosine transform/inversed discrete cosine transform (DCT/IDCT). One is changeable input/output format presented by DCT/IDCT when it deals with TUs of different sizes, which intensifies the nonconformity during the data exchange with other modules. The other is the demand for high throughput to traverse the vast possible TU partitions to find the best one, which would be easily dragged by an inefficient data exchange method. To solve this problem, a parallel-access data mapping method based on single-port static random access memory devices (SRAMs) is proposed in this brief. It can be applied to the data exchange buffers around DCT/IDCT in HEVC encoders to fulfill a high-throughput data exchange. Here, parallel access means one row of 1 $\times$ 32 pixels, two rows of 1 $\times$ 16 pixels, four rows of 1 $\times$ 8 pixels, or four rows of 1 $\times$ 4 pixels could be accessed in one cycle depending on the specific size of the current TU.

Si and InGaAs Spatial Wavefunction-Switched (SWS) FETs with II–VI Gate Insulators: An Approach to the Design and Integration of Two-Bit SRAMs and Binary CMOS Logic

Electron wavefunctions are switched spatially from one quantum well to another by varying the gate voltage Vg in spatial wavefunction-switched (SWS) field-effect transistors (FETs), which comprise two or more coupled quantum wells serving as the transport channel. This is shown for Si/SiGe and InGaAs/AlInAs quantum well systems. The presence of charge in a particular well or channel is used to encode four states 00, 01, 10, 11. This unique property is used for two-bit processing, resulting in compact two-bit static random-access memory devices. Experimental data including capacitance–voltage peaks in Si and InGaAs multiple quantum well SWS-FETs has verified the SWS phenomenon. Replacing quantum wells by an array of cladded quantum dots, forming a quantum dot superlattice (QDSL) layer, enhances the contrast and noise margin in SWS-FETs. This paper reports I–V and C–V characteristics for a fabricated twin-drain SWS-quantum dot channel (QDC) FET comprising four layers of self-assembled SiOx-Si quantum dots. SWS-QDC-FETs are shown to be scalable to ∼9 nm, and comprise four layers of cladded quantum dots with an array of 3 × 3 forming the channel.

Theoretical and practical approach to overcome curvature radius limitation of conductive atomic force microscopy tip for imaging of advanced technological node static random access memory devices

This paper demonstrates a methodology to overcome the challenges in obtaining a distinguishable current image when the radius of curvature of the conductive atomic force microscopy (C-AFM) tip is larger than the feature size of the device under test, e.g., the individual tungsten contacts of a static random access memory (SRAM) device. A model is presented to understand the interaction between the C-AFM tip and the features on the surface of a SRAM sample. Based on this model, recessed depth (tungsten recessed to neighboring dielectric) or protruding height (protruding tungsten with respect to the dielectric) is then created on the sample surface to provide suitable topographical contrast so that the electrical signals from the smaller tungsten contacts could be better discerned. It has been calculated that the surface treated dimensions need to fall within a feasible range in order to obtain a well-resolved current image. In the case where a recessed depth is created, the depth cannot be too deep as the edge of the neighboring insulating dielectric would block the base of the C-AFM tip and prevent the tip from accessing the lower-residing tungsten contact. The lack of good contact between the tip and receding tungsten contact would result in the inability to extract the electrical signals from the tungsten contact. In the case where protruding tungsten is created, a height limit exists whereby the conductive-AFM tip would unintentionally touch the neighboring tungsten contacts, creating a false illusion that the tungsten contacts are shorted together. The proposed model is generic and is able to serve as a guide to achieve a good current image. The required dimension could be easily calculated by inserting the known specifications into the model. Following the theoretical understanding, the recessed depth and protruding height are then physically created on the sample surface for enhanced C-AFM imaging. The experimental results agree well with the theoretical predictions from the model. This technique is then applied on actual failure analysis/fault isolation of SRAM devices.

Unexpected surface implanted layer in static random access memory devices observed by microwave impedance microscope

Real-space mapping of doping concentration in semiconductor devices is of great importance for the microelectronics industry. In this work, a scanning microwave impedance microscope (MIM) is employed to resolve the local conductivity distribution of a static random access memory sample. The MIM electronics can also be adjusted to the scanning capacitance microscopy (SCM) mode, allowing both measurements on the same region. Interestingly, while the conventional SCM images match the nominal device structure, the MIM results display certain unexpected features, which originate from a thin layer of the dopant ions penetrating through the protective layers during the heavy implantation steps.

Feasibility Study of $\hbox{Mo/SiO}_{x}/\hbox{Pt}$ Resistive Random Access Memory in an Inverter Circuit for FPGA Applications

We proposed a Mo/SiO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">x</sub> /Pt resistive random access memory (RRAM) device as an alternative to static random access memory (SRAM) devices for field-programmable gate array (FPGA) applications. In order to evaluate the feasibility of our RRAM device for FPGA applications, we utilized an RRAM device + inverter structure and confirmed its successful operation under various operational schemes, multilevel operation by controlling bias condition, and immunity against read disturbance and a retention test at high temperature. From the nonvolatile and reliable characteristics of our RRAM device, unlike that of SRAM devices, it holds promise to enable reconfigurable logic applications with significantly reduced logic-gate density and power consumption.

Quantitative measurement of voltage contrast in scanning electron microscope images for in-line resistance inspection of wafers

We develope an in-line inspection method for partial-electrical measurement of defect resistance, which is quantitatively estimated from the voltage contrast formed in a scanning electron microscopy (SEM) image of an incomplete-contact defect. We first manufacture standard calibration wafers for the voltage-contrast calibration. The contact resistance of systematically formed defects varied from 108 to 1017 . Then, we quantitatively analyze the gray scales of these defect images captured using a review SEM. As a result, calibration curves for estimating the contact resistance of the incomplete-contact defect are obtained at a probe current of 60 pA and a charging voltage of 4 V. The estimated contact resistance is between 107 and 1012 . Finally, this inspection method is applied to wafers manufactured for a static random access memory device. Accordingly, the gray scales of defective plugs formed for shared contact patterns are classified into two levels. The resistances of these defects are estimated from the calibration curve. The estimated resistances of the lower contrast defects (with an accuracy of about one order of magnitude) agree well with the resistances measured using a nanoprober. The resistances of the higher contrast defects are estimated as well, although they are too high to be measured using a nanoprober.

Yield improvement of 0.13μm Cu/low-k dual-damascene interconnection by organic cleaning process

Cu/low-k dielectrics are required to reduce resistance-capacitance (RC) delay and parasitic capacitance at the back-end-of-line (BEOL) interconnection. Integration of Cu/low-k dielectrics (black diamond) for BEOL interconnection in 0.13μm technology has gained wide acceptance in the microelectronics industry in recent years. In this article, the authors discuss the process-integration issues of 0.13μm Cu/low-k dual-damascene integration for static random access memory (SRAM) device yield. The same scheme of 0.13μm Cu/fluorinated silicate glass–based device was used for the full process of making a low-k based device. Black diamond was used as a low-k material with a dielectric constant of 2.95. To reduce the damage of low-k and improve the yield of a low-k based device, H2O ashing, organic cleaning, and reduced down pressure in chemical-mechanical planarization were selected for the study. Specifically, the cleaning process after the ashing process was very effective for the removal of organic residues from via, trench, and surface contaminants. There was an increase of 40.79% in SRAM device yield compared to the low-k based device without the organic cleaning chemical process. As a result, the authors successfully integrated a 0.13μm Cu/low-k dual-damascene interconnection with excellent yield performance after the improving process of organic cleaning.

Mechanism of Increase in SRAM $V_{\min}$ Due to Negative-Bias Temperature Instability

Negative-bias temperature instability (NBTI) has been identified as a problem for static random-access-memory (SRAM) reliability since variations in the PMOS threshold voltages have been shown to correlate with rising V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">min</sub> over time. The effect is greater than what would be expected from the relatively low sensitivity of the static-noise margin to PMOS device parameters reported in the literature. This paper investigates the mechanism of V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">min</sub> increases due to NBTI. It is shown that the sensitivity to PMOS threshold voltages increases at low voltages, and furthermore, this sensitivity can be exacerbated by process variations in other SRAM devices. For the design of an array with many cells, the most probable combination of parameter variations to set a given V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">min</sub> is identified and shown to change to a more probable combination with NBTI. Statistical designs must therefore consider NBTI as an additional source of variation, with increasing significance at low voltages.

소프트 에러율에 대한 박막 트랜지스터형 정적 RAM의 신뢰성

We investigated accelerated soft error rate (ASER) in static random access memory (SRAM) cells of thin film transistor (TFT) type. The effects on ASER by cell density, buried nwell structure, operational voltage, and polysilicon-2 layer thickness were examined. The increase in the operational voltage, and the decrease in the density of SRAM cells, respectively, resulted in the decrease of ASER values. The SRAM chips with buried nwell showed lower ASER than those with normal well structure did. The ASER decreased as the test distance from alpha source to the sample increased from . As the polysilicon-2 thickness increased up to , the ASER decreased exponentially. In conclusion, the best condition for low soft error rate, which is essential to obtain highly reliable SRAM device, is to apply the buried nwell structure scheme and to fabricate thin film transistors with the thick polysilicon-2 layer

Extending aggressive low-k1 design rule requirements for 90 and 65 nm nodes via simultaneous optimization of numerical aperture, illumination and optical proximity correction

It has been a challenge for the lithography process to meet aggressive integrated circuit design rule requirements for 90 nm and upcoming 65 nm technology nodes under low-k1 patterning constraints. The geometric design rules are largely governed by numerical aperture (NA), illumination settings, and optical proximity correction (OPC) for any resolution enhancement technique-applied mask. A set of process feasible design rule criteria is explored based on state-of-the-art microprocessor chip that contains three different types of circuit design-standard library cell (SLC), random logic (RML), and static random access memory (SRAM). The critical design rule criteria to keep higher packing density for SRAM involve: achievable minimum pitch, sufficient area of contact-landing pad, minimum line-end shortening (LES) to ensure poly end-cap and preferably optimum pitch for placement of Scattering BarTM (SB). The goal is to achieve printing of ever-smaller critical dimension (CD) with greater CD uniformity control for RML. SLC should be designed with comparable criteria to both RML and SRAM devices. Hence, the design rule constraints for CD, space, line-end, minimum pitch and SB placement for SLC cell are critically confined. Unlike traditional method of assuming a linear scaling for the design rule set, achievable design rule criteria is explored for very low k1-imaging by simultaneously optimizing NA, illumination settings and OPC (for optimum placement of SB) for a calibrated process. This is done by analyzing CD uniformity control and maximum overlapped process window for critical lines, spaces and line-ends with the respective k1 factor for three types of circuits. A feasible set of design rules for 90 nm node with k1 as low as 0.36 can be obtained using 6% attenuated phase shift mask (attPSM) with 6% exposure latitude at 400 nm of overlapped depth of focus.

Development of self-aligned contact technology for 0.18 μm static random access memory devices

A self-aligned contact (SAC) technology is developed for the application of electrical contacts between the local interconnect and the silicon diffusion regions for 0.18 μm static random access memory cells. The key components of this SAC technology include the deposition and gap fill of borophosphosilicate glass (BPSG) films, a selective oxide etch process, and metal-plug contact formation by Ti/TiN-liner silicidation and W filling. The BPSG film, deposited by plasma enhanced chemical vapor deposition, has exhibited an ability of filling 0.04 μm spaces with an aspect ratio (AR) of about 10:1 after reflow at 800 °C. Reduction of the reflow temperature without gap-fill deterioration by increasing the B incorporation in the BPSG film is not feasible due to an increase of BPSG defects. The oxide SAC etch performance is modulated by an oxide-to-nitride etch selectivity which has shown a strong dependence on the wafer temperature. The etch process window is improved by optimization of the process conditions including the wafer temperature uniformity. A novel SAC etch process was demonstrated for an ∼0.2 μm SAC opening. The electrical performance of a contact with an AR as high as 10:1 has met the design requirement, which has indicated sufficient liner silicidation and an excellent W plug process. Investigation of the contact resistance dependence on the contact AR has shown a reduction in contact resistance with increasing AR. All these findings are very instructive for our development projects.

Optimization of Multilayer Thin Film Passivation Processes for Improving Cache Memory Device Performance

A multilayer thin film passivation structure based on alternating plasma‐enhanced chemical vapor deposited (PECVD) layers are prepared and characterized, in order to improve and optimize the electrical performance and hot carder reliability of polyload resistors in 4‐transistor (4‐T) cache static random access memory devices. gas mixtures are utilized as precursors for oxide CVD process. Adopting a higher flow rate ratio during deposition renders the resulting oxide films more silicon rich, as manifested by their higher refractive index (RI) and wet etch rates. These modifications in film characteristics are also accompanied by enhanced resistance of polyload resistor and lower percentage hot‐carrier linear drain current degradation. An increase in RI from 1.46 to 1.67 translates to a rise in resistance of polyload resistor from 98 to 225 GΩ and a fall in from 5.8 to 4.5%. Further improvement in device performance can be realized by modifying the stoichiometry of the overlying nitride passivation layer. This is achieved by increasing bias power while reducing the gas flow rate ratio during the PECVD nitride deposition process. The nitride films thus deposited contain lower Si‒H bond density, and exhibit lower buffered oxide etch rates and compressive stress. Passivation structures based on the combination of a high RI oxide and a low Si‒H content nitride layers yield the most promising device performance and reliability. Defect species in the oxide passivation layer are identified and their charge trapping mechanisms clarified. Impact of moisture and hydrogen from the passivation on polygate and load resistor are both held responsible for device degradation. Interfacial defect reactions involving both hydrogen and moisture are proposed to account for the carrier trapping mechanisms responsible for device failure. © 1999 The Electrochemical Society. All rights reserved.