Optimization of Multilayer Thin Film Passivation Processes for Improving Cache Memory Device Performance

Abstract

A multilayer thin film passivation structure based on alternating plasma‐enhanced chemical vapor deposited (PECVD) layers are prepared and characterized, in order to improve and optimize the electrical performance and hot carder reliability of polyload resistors in 4‐transistor (4‐T) cache static random access memory devices. gas mixtures are utilized as precursors for oxide CVD process. Adopting a higher flow rate ratio during deposition renders the resulting oxide films more silicon rich, as manifested by their higher refractive index (RI) and wet etch rates. These modifications in film characteristics are also accompanied by enhanced resistance of polyload resistor and lower percentage hot‐carrier linear drain current degradation. An increase in RI from 1.46 to 1.67 translates to a rise in resistance of polyload resistor from 98 to 225 GΩ and a fall in from 5.8 to 4.5%. Further improvement in device performance can be realized by modifying the stoichiometry of the overlying nitride passivation layer. This is achieved by increasing bias power while reducing the gas flow rate ratio during the PECVD nitride deposition process. The nitride films thus deposited contain lower Si‒H bond density, and exhibit lower buffered oxide etch rates and compressive stress. Passivation structures based on the combination of a high RI oxide and a low Si‒H content nitride layers yield the most promising device performance and reliability. Defect species in the oxide passivation layer are identified and their charge trapping mechanisms clarified. Impact of moisture and hydrogen from the passivation on polygate and load resistor are both held responsible for device degradation. Interfacial defect reactions involving both hydrogen and moisture are proposed to account for the carrier trapping mechanisms responsible for device failure. © 1999 The Electrochemical Society. All rights reserved.