Mechanism of Increase in SRAM $V_{\min}$ Due to Negative-Bias Temperature Instability

Abstract

Negative-bias temperature instability (NBTI) has been identified as a problem for static random-access-memory (SRAM) reliability since variations in the PMOS threshold voltages have been shown to correlate with rising V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">min</sub> over time. The effect is greater than what would be expected from the relatively low sensitivity of the static-noise margin to PMOS device parameters reported in the literature. This paper investigates the mechanism of V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">min</sub> increases due to NBTI. It is shown that the sensitivity to PMOS threshold voltages increases at low voltages, and furthermore, this sensitivity can be exacerbated by process variations in other SRAM devices. For the design of an array with many cells, the most probable combination of parameter variations to set a given V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">min</sub> is identified and shown to change to a more probable combination with NBTI. Statistical designs must therefore consider NBTI as an additional source of variation, with increasing significance at low voltages.