Si and InGaAs Spatial Wavefunction-Switched (SWS) FETs with II–VI Gate Insulators: An Approach to the Design and Integration of Two-Bit SRAMs and Binary CMOS Logic

Abstract

Electron wavefunctions are switched spatially from one quantum well to another by varying the gate voltage Vg in spatial wavefunction-switched (SWS) field-effect transistors (FETs), which comprise two or more coupled quantum wells serving as the transport channel. This is shown for Si/SiGe and InGaAs/AlInAs quantum well systems. The presence of charge in a particular well or channel is used to encode four states 00, 01, 10, 11. This unique property is used for two-bit processing, resulting in compact two-bit static random-access memory devices. Experimental data including capacitance–voltage peaks in Si and InGaAs multiple quantum well SWS-FETs has verified the SWS phenomenon. Replacing quantum wells by an array of cladded quantum dots, forming a quantum dot superlattice (QDSL) layer, enhances the contrast and noise margin in SWS-FETs. This paper reports I–V and C–V characteristics for a fabricated twin-drain SWS-quantum dot channel (QDC) FET comprising four layers of self-assembled SiOx-Si quantum dots. SWS-QDC-FETs are shown to be scalable to ∼9 nm, and comprise four layers of cladded quantum dots with an array of 3 × 3 forming the channel.