Static Random Access Memory Circuit Research Articles

Application of machine learning to SRAM circuit design

This paper discusses the application of machine learning in Static Random Access Memory (SRAM) circuit design. It mentions several aspects of application analysis, including SRAM design for machine learning applications, SRAM PUF design for machine learning modelling attacks, lightweight fault-tolerant mechanism for NVDLA-based edge AI chips, interconnection resource allocation of SRAM FPGAs using reinforcement learning and Markov decision process, and SRAM power optimization and privacy security using machine learning. This article conclude that machine learning can be used to model and optimize SRAM performance, improve system reliability and stability through fault detection and fault tolerance mechanisms, provide a more comprehensive and efficient approach to testing and verification, and automatically correct and repair errors. The significance of machine learning in SRAM design is to provide an intelligent method and tool that can speed up the design process, improve system performance, increase reliability, and drive the advancement of chip manufacturing and processes.

Hybrid CMOS and Pseudo-CMOS Organic Memory for Flexible Sensors

In this paper, we propose and elucidate a novel static random access memory (SRAM) for flexible electronic systems using low-voltage organic thin-film transistors. The SRAM can be used for local data storage and post-processing of the signals generated by sensors. This is essential for truly flexible systems. The proposed SRAM utilizes hybrid CMOS and pseudo-CMOS design to enhance stability. The memory cells based on CMOS design style utilize p-type access transistors to improve area efficiency and stability. A degradation-mitigation circuit, based on pseudo-CMOS design style, extends retention time. The proposed circuit, which is comprised of few basic logic gates, is easy to implement and occupies minimum layout area. The SRAM circuit can self-detect degradation and automatically perform a process to mitigate device degradation at the necessary time periods.We confirm the operation of key components in the proposed memory via test chip measurements. Additionally, the effectiveness of the degradation-mitigation circuit has been verified.

Propagation Delay and Power Dissipation Analysis for a 2-Bit SRAM Using Multi-State SWS Inverter

This paper presents a study on the propagation delay and power dissipation of a 2-bit static random-access memory (SRAM) with two cross-coupled multi-state spatial wave function switching (SWS) CMOS inverters. The proposed SRAM design utilizes the advantages of the CMOS-SWS inverter, such as its small area, low power consumption, and high speed. The 2-bit SRAM circuit simulations were carried out in Cadence to analyze the power dissipation and propagation delay. An Analog Behavioral Model (ABM) and the Berkeley Short-channel IGFET Model (BSIM4.6) in 0.18-μm technology were combined to create this model. The analysis of the propagation delay shows that the multi-state CMOS-SWS SRAM significantly reduces the delay compared to other multi-state 6T SRAM memories. Additionally, the analysis of the power dissipation shows that the multi-state SWS-SRAM is comparable to conventional SRAMs. These results demonstrate the potential of multi-state SWS-SRAM for improving the performance of memory circuits and provide valuable insights for future design optimization.

Cross-Coupled Gated Tunneling Diodes With Unprecedented PVCRs Enabling Compact SRAM Design—Part II: SRAM Circuit

In Part I of this article, we present a novel device, i.e., a cross-coupled gated tunneling diode (XTD), which exhibits negative differential resistance (NDR) with peak-to-valley current ratios (PVCRs) exceeding 105. In this part of this article, based on the XTD, we introduce a compact static random access memory (SRAM) cell using a one-transistor and two-XTD (1T-2X) design. The layout of the SRAM cell as well as a detailed analysis of the cell behavior and SRAM array performance are presented. In particular, our simulation results show that the 1T-2X SRAM cell can achieve <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$70\times $ </tex-math></inline-formula> improvement in standby power with ~ <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$8\times $ </tex-math></inline-formula> area reduction compared to standard CMOS SRAM.

An Ultra-Low-Voltage Bit-Interleaved Synthesizable 13T SRAM Circuit

Standard-cell-based memory (SCM) circuits with fully digital signals are attractive for power-/energy-constrained edge devices due to the strong voltage scaling capability, fast design iteration, and flexibility in integration. In this article, a 13-transistor (13T) static-random access memory (SRAM) circuit with ultra-wide range voltage scaling capability is proposed for ultra-low-power applications. By adopting the concept of SCM, the 13T SRAM cell is custom-designed, while providing fully digital inputs and outputs. Without any analog circuitry, the 13T memory array is fully synthesizable and compatible with the commercial semi-custom design flow. A specialized circuitry is employed in the 13T SRAM cell to enable cell-level bit-interleaving. An 8-kb 13T SRAM bank is fabricated in the UMC 55-nm low power CMOS technology, achieving an area density of <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$5 \mu \text{m}$ </tex-math></inline-formula> 2/bit. The minimum operational voltage for the 13T SRAM circuit is 324 mV, while the data retention voltage is down to 279 mV. The 13T SRAM circuit achieves the minimum energy point at 0.4 V for both the read (32.8 fJ/bit) and write (54.1 fJ/bit) operations, providing a good opportunity to perform voltage scaling together with logic blocks when embedded in the same power domain.

Simulation of transient radiation upset in a 0.18-μm CMOS SRAM by accurately modeling a 6T memory cell

Static random-access memory (SRAM) circuits exposed to pulsed X- or γ-rays will suffer transient radiation upsets, which poses a significant challenge to their reliability. The transient radiation upsets are caused by global photocurrents, which are governed by the interconnect resistance of the power supply lines and the local photocurrents generated in each memory cell. Thus, accurate modeling of local photocurrents in each memory cell is essential for predicting the global photocurrents and transient radiation upset thresholds of SRAM circuits. In this study, the local photocurrents generated in a 0.18-μm complementary metal-oxide-semiconductor (CMOS) SRAM cell are extracted using a physics-based model of the actual device structure, rather than an analytical or experimental model. The memory cell containing six transistors and parasitic structures is accurately modeled in three-dimensions. Its responses to pulsed γ-rays are simulated with an in-house parallel semiconductor device simulation program, which enables the extraction of accurate local photocurrents. These local photocurrents, together with the interconnect resistance of the power supply lines in SRAM circuits, are modeled and simulated with an in-house parallel SPICE circuit solver. Using this approach, the global photocurrents in the 0.18-μm CMOS SRAM circuit irradiated with γ-rays are obtained and the known rail-span-collapse effect is observed. Finally, the transient radiation upset threshold of the SRAM circuit is predicted numerically and verified experimentally.

Back gate impact on SEU characterization of a Double SOI 4k-bit SRAM

In this paper, heavy-ion single-event effects studies are investigated on a 0.2 μm Double silicon-on-insulator (DSOI) 4k bit Static Random Access Memory (SRAM). The back gate bias is used to adjust the single event upset (SEU) rate of the SRAM circuit. Experimental results show that applying a -5 V bias to the back gate of nMOSFETs can reduce the SEU cross section by 31 % ~ 62 %, and the SEU rate by 61 %. While applying to the back gate of both nMOSFETs and pMOSFETs a 5 V bias can increase the SEU cross section by 43 % ~ 298 %, and the SEU rate by 3 orders of magnitude. The SEU rate is calculated using OMERE software under the GEO orbit with a 3 mm aluminum shielding condition. To further analyze the cause of this phenomenon, TCAD simulation and DSOI MOSFETs test were introduced in this paper. Results show that applying a negative bias to the back gate of nMOSFETs will reduce the single particle transient (SET) and increase the threshold voltage of nMOSFETs, which makes the SRAM cell more tolerant to SEU; while applying a positive bias to the back gate of pMOSFETs will decrease the drive current of pMOSFETs, which makes the SRAM cell more sensitive to SEU.

A Novel STT–SOT MTJ-Based Nonvolatile SRAM for Power Gating Applications

This article proposes novel nonvolatile (NV) static random access memory (SRAM) circuits based on spin transfer torque (STT) and spin orbit torque (SOT) operated magnetic tunnel junction (MTJ) device for energy-efficient power gating circuits. In which, two different designs of 9T-2MTJs and 10T-2MTJ-based NV SRAM circuits are proposed for low power, high noise margin, and faster switching speed with less area overhead. The proposed architecture uses a smaller number of transistor combinations to accommodate low-power operation with compact cell size when compared with available pieces of literature. Also, the combination of nMOS and pMOS transistors in the proposed architecture enhances the driving capability of the circuit for both low and high input operations. Here, the electrical characteristics of the proposed designs have been compared and contrasted with the available 11T-2MTJ and 7T-2D-2MTJ non volatile static random access memory (NVSRAM) and 6T SRAM circuits using a UMC-40 nm design kit and physics-based STT–SOT MTJ Verilog-A Model. The proposed 9T-2MTJ-based NVSRAM was found to be a better alternative and offers improved performance in terms of higher restore noise margin and lower power consumption than other circuits reported at this node. Moreover, the studied 10T-2MTJ exhibits an improved write and hold noise margin than the proposed/available 9T/7T-2D/11T-2MTJ circuits.

Evaluation of total-ionizing-dose effects on reconfigurable field effect transistors and SRAM circuits

For the first time, this paper presents a qualitative analysis of the total-ionizing-dose effects on reconfigurable field effect transistors (RFETs) and the corresponding static random-access memory (SRAM) circuits based on 3D technology computer aided design simulations. The effects of various electrical biases and geometric parameters are investigated in detail. For n- and p-type programs, the threshold voltages (V TH) respectively decrease by 83 mV and increase by 57 mV after 40 Mrad (Si) of irradiation. Radiation-induced oxide trap charges in the spacer region near the source side are shown to mainly dominate the performance degradation in RFETs. The control gate voltage (V CG) and spacer length on the source side L S_Spacer are shown to have a significant influence on the total-ionizing-dose response, and a shorter L S_Spacer presents a stronger total-dose tolerance. When the RFETs in SRAMs suffer from a degraded V TH, the SRAM’s read static noise margin declines by 51.3 mV after 40 Mrad (Si) of irradiation. This work provides a radiation hardening foundation for the application of RFET technology in future extreme-environment electronics applications.

Investigation of process variation in vertically stacked gate-all-around nanowire transistor and SRAM circuit

An investigation into the intrinsic process variations including random dopant fluctuation (RDF), interface trap fluctuation, work-function variation (WFV) and oxide thickness variation was undertaken in a vertically stacked gate-all-around nanowire transistor. The fluctuation of the electrical characteristics induced by different sources of variation was discussed. The impact of process variations on static random access memory (SRAM) was also studied. On-state current could be affected by RDF in the source and drain region and the standard deviation can reach 17.2% of the median. WFV can cause obvious fluctuations in threshold voltage and consequently in the read static noise margin (RSNM) of SRAM. It has been discovered that the RSNM was deteriorated by 6.8% by WFV, which causes great uncertainty among all variation sources.

High-Density SRAM Read Access Yield Estimation Methodology

As high-density SRAMs must be designed to ensure a substantially small failure rate, the accurate yield estimation with practically acceptable runtime of circuit simulations is highly challenging. Here, a read access yield estimation method for high-density static random access memory (SRAM) is proposed. Instead of performing SPICE runs for the entire SRAM circuit, the proposed method partitions the SRAM into three parts—the control signal generation circuit, bitcell array, and sense amplifier (SA)—that determine three key parameters: word-line to SA enable delay, bit-line voltage difference, and SA offset voltage. Subsequently, the proposed method derives the probability density of these key parameters from each of the three partitioned circuits. Here, different methods are applied to derive the probability of the key parameters, considering the respective characteristics of each circuit part and parameter. According to our experimental results, the proposed method can accelerate the yield estimation by 500– $3000\times $ , compared with the brute-force Monte Carlo simulation method, and 10– $100\times $ compared with the other state-of-art methods. In addition, the proposed method can accelerate the circuit optimization procedure accompanied by multiple circuit revisions, that is, the circuit revisions can be reflected with SPICE runs only for the revised circuit part, unlike the previous methods that require SPICE runs for the entire SRAM.

A Spline-High Dimensional Model Representation for SRAM Yield Estimation in High Sigma and High Dimensional Scenarios

Traditional Static Random-Access Memory (SRAM) yield estimation through Monte Carlo analysis is an extremely time-consuming process since it runs millions of expensive transistor-level simulations to get the yield results with the specified precision, especially for the large-scale circuits. In this paper, we develop an efficient yield analysis framework by integrating our novel performance metamodel into a state-of-art importance sampling method. The performance meta-model, named Spline-High Dimensional Model Representation (SP-HDMR), is used to substitute the expensive transistor-level simulations in yield estimation. The proposed SP-HDMR model provides a high computationally efficient formula expansion. It uses spline functions as the kernels to describe the various relations between the process parameters and SRAM read access delay. And an adaptive sampling method with sparsity analysis is developed to support SP-HDMR modeling. The experiments on the 40nm SRAM circuits validate the accuracy and the efficiency of the proposed yield analysis framework based on our SP-HDMR model with 1.3X $\sim 5\text{X}$ speedup over the other state-of-art methods within 9% relative error.

Monolithic 3D Carbon Nanotube Memory for Enhanced Yield and Integration Density

Carbon nanotube field effect transistor (CN-MOSFET) is attractive for the realization of future monolithic three-dimensional (M3D) memory circuits with ultra-high integration density, capacity, efficiency, and speed. However, the yield of each vertically-stacked active layer can be significantly degraded by the presence of metallic carbon nanotubes (m-CNs) caused by process imperfections. The potential integration density benefits of M3D circuits also may not be fully realized by the large area skews between different layers within standard cells. In this paper, ultra-high density and robust M3D static random-access memory (SRAM) cells are proposed for tolerance to the removal of m-CNs. By minimizing the skew and area of each device layer, the 16Kibit memory arrays with the proposed SRAM cells enhance the integration density by up to 82.92% as compared to the carbon-based traditional 2D and previously published M3D memory arrays. While achieving high functional yield and maintaining robust read/write operations, the proposed SRAM circuits enhance the overall electrical quality by up to 27.41x as compared to the alternative 2D and M3D memory arrays.

SRAM With Buried Power Distribution to Improve Write Margin and Performance in Advanced Technology Nodes

This letter proposes for the first time buried powered static random-access memory (SRAM) to achieve enhanced write margin and performance in advanced CMOS technology nodes. The buried power rail (BPR) for SRAM is silicon verified. The BPR helps to lower the bitline and wordline resistance by relaxing metal width in SRAM circuits and thereby enhances the write margin and performance. The proposed SRAM provides up to 340 mV and 30.6% improvement in write margin and read speed, respectively, as compared to its conventional counterpart without incurring any area penalty in a hardware influenced 3 nm CMOS technology.

Reliability and Energy Efficiency of the Tunneling Transistor-Based 6T SRAM Cell in Sub-10 nm Domain

The static random access memory (SRAM) has a significant impact on the overall power consumption and energy efficiency of any micro and nanoelectronics application or system. SRAM consumes a considerable amount of power in the idle state. As a consequence, the leakage power is one of the most critical metrics in SRAM designs. This brief evaluates the standby leakage power in the tunnel FET (TFET)-based 6T SRAM cell for different pull-up, pull-down, and pass-gate transistors ratios (PU: PD: PG) and compared to 10-nm FinFET-based 6T SRAM designs. It is observed that the 10-nm TFET-based SRAMs have 60.7, 65.22, and 59.7 times less standby leakage power compared to the 10-nm FinFET-based SRAMs when the PU: PD: PG ratios are 1:1:1, 1:5:2, and 2:5:2, respectively. This brief also presents an analysis of the stability and reliability of TFET-based 6T SRAM circuit with a reduced supply voltage of 500 mV. The static noise margin, which is a critical measure of SRAM stability and reliability, is determined for hold, read and write operations of the 6T TFET SRAM cell. The robustness of the optimized TFET-based 6T SRAM circuit is also evaluated at different supply voltages. Simulations were done in HSPICE and cadence tools.

The impact of scaling on single event upset in 6T and 12T SRAMs from 130 to 22 nm CMOS technology

ABSTRACTAs transistor sizes scale down to nanometres dimensions, CMOS circuits become more sensitive to radiation. High-performance static random access memory (SRAM) cells are prone to radiation-induced single event upsets (SEU) which come from the natural space environment. The SEU generates a soft error in the transistor due to the strike of an ionizing particle. Thus, this paper compares the endurance of 12T SRAM and 6T SRAM circuit on 130 up to 22 nm CMOS technology towards SEU. Besides that, this paper discusses the trend of critical linear energy transfer (LET) and collected charge due to technology scaling for the respective circuit. The critical LET (LETcrit) and critical charge (Qcrit) of 6T are approximately 50% lower compared with 12T SRAMs.

Spatial Wavefunction Switched (SWS) FET SRAM Circuits and Simulation

This paper presents the design and simulation of static random access memory (SRAM) using two channel spatial wavefunction switched field-effect transistor (SWS-FET), also known as a twin-drain metal oxide semiconductor field effect transistor (MOS-FET). In the SWS-FET, the channel between source and drain has two quantum well layers separated by a high band gap material between them. The gate voltage controls the charge carrier concentration in the quantum well layers and it causes the switching of charge carriers from one channel to other channel of the device. The standard SRAM circuit has six transistors (6T), two p-type MOS-FET and four n-type MOS-FET. By using the SWSFET, the size and the number of transistors are reduced and all of transistors are n-channel SWS-FET. This paper proposes two different models of the SWS-FET SRAM circuits with three transistors (3T) and four transistors (4T) also addresses the stability of the proposed SWS-FET SRAM circuits by using the N-curve analysis. The proposed models are based on integration between Berkeley Shortchannel IGFET Model (BSIM) and Analog Behavioral Model (ABM), the model is suitable to investigate the gates configuration and transient analysis at circuit level.

High-Yield and Robust 9T SRAM Cell Tolerant to Removal of Metallic Carbon Nanotubes

Metallic carbon nanotubes (m-CNs) cause malfunction by shorting the source and drain terminals in carbon nanotube transistors. To achieve high-yield with robust read and write operations, a new nine carbon nanotube MOSFET (9-CN-MOSFET) static random-access memory (SRAM) cell that can tolerate the removal of m-CNs is proposed in this paper. A functional yield model considering the spatial correlations of carbon nanotubes in channel arrays of CN-MOSFETs is developed. The yield of the m-CN-removal-tolerant 9-CNMOSFET SRAM array is increased by 21309× as compared to a design that does not consider process imperfections in carbon-based electronics. Due to the increased strength of read and write ports, the read delay and worst-case write delay of the m-CN-removal-tolerant 9-CN-MOSFET SRAM circuit are reduced by 29.05% and 22.30%, respectively, as compared to the previously published memory circuit that does not consider process imperfections in a 16-nm CN-MOSFET technology.

Subthreshold FinFET SRAM at 20nm Technology with Improved Stability and Lower Leakage Power

Background/Objectives: The Complementary Metal–Oxide–Semiconductor (CMOS) scaling feature was the wonderful feature which led the electronics market into in an era of miniaturization but with the fascinating feature some limitations has also been observed. Methods/Statistical analysis: CMOS technology has also given a new horizon to the memory circuits like Static Random-Access Memory (SRAMs). To overcome the limitations of scaling of the CMOS technology, Fin Field Effect Transistor (FinFET) technology has been chosen. To overcome the limitations of scaling of the CMOS technology, FinFET technology has been chosen. Like CMOS SRAMs, FinFET SRAMs have also gained popularity because of the advantages as discussed in this paper. Findings: In this paper, FinFET SRAM cells have been proposed in three different configurations for better stability and reduced leakage power in sub threshold region at 20nm technology.4 different modes of FinFET has been used to implement the SRAM. The FinFETs are classified as (i) SG-mode (ii) LP-mode and (iii) IG mode. A comprehensive analysis has been made for all the 4 types of SRAM stability which includes for Read Margin, Write Margin, Hold Margin and leakage power analysis by finding the leakage current for all the proposed circuits and has compared with the previous work and it has been found that the proposed circuits serves better in terms of stability and reduced leakage current. The cell has been implemented for sub threshold voltages ranging from 0.4V to 0.1V. The maximum Write Margin at 0.4V is 196.9mV, Read Margin is 110 mV. Application/Improvements: It has been found that from the different SRAM circuits, IG-P has the maximum Write SNM, Read SNM and hold margin while LP mode has minimum leakage current, next the IG-P mode FinFET.

ANALYSIS OF STATIC NOISE MARGIN FOR NOVEL POWER GATED SRAM

Data stability is one of the important parameter of SRAM with scaling of CMOS technology. However the move to nanometer technology not only nodes has increased, but the variability in device characteristics has also increased due to large process variations. Static random access memory (SRAM) is a popular component which is used in modern microprocessors and occupies a considerable chip area. It is useful to store the data as well as read and write operation. The performance of SRAM circuit is measured with data stability and read-write SNM (Static Noise Margin). A novel power gated SRAM cell is presented in this paper with enhanced data stability and reduced leakage power. The data becomes completely isolated form bit line during read operation in new power gated SRAM. The SNM of the new power gated cell is thereby increased by 2 times in comparison to a conventional six transistor (6T) SRAM cell. The paper also covers the comparative analysis and simulation of both SRAM cell on the basis of Read Noise Margin and Write Noise Margin. The novel power gated SRAM cell has larger read and write SNM as compared to conventional 6T SRAM cell at different technologies. All results are carried out on 45nm, 32nm and 22nm CMOS technology using HSPICE simulation tool.