A Spline-High Dimensional Model Representation for SRAM Yield Estimation in High Sigma and High Dimensional Scenarios

Liang Pang,Shan Shen,Mengyun Yao

doi:10.1109/access.2021.3067510

Liang Pang, Shan Shen + Show 1 more

Open Access

https://doi.org/10.1109/access.2021.3067510

Copy DOI

Abstract

Traditional Static Random-Access Memory (SRAM) yield estimation through Monte Carlo analysis is an extremely time-consuming process since it runs millions of expensive transistor-level simulations to get the yield results with the specified precision, especially for the large-scale circuits. In this paper, we develop an efficient yield analysis framework by integrating our novel performance metamodel into a state-of-art importance sampling method. The performance meta-model, named Spline-High Dimensional Model Representation (SP-HDMR), is used to substitute the expensive transistor-level simulations in yield estimation. The proposed SP-HDMR model provides a high computationally efficient formula expansion. It uses spline functions as the kernels to describe the various relations between the process parameters and SRAM read access delay. And an adaptive sampling method with sparsity analysis is developed to support SP-HDMR modeling. The experiments on the 40nm SRAM circuits validate the accuracy and the efficiency of the proposed yield analysis framework based on our SP-HDMR model with 1.3X $\sim 5\text{X}$ speedup over the other state-of-art methods within 9% relative error.

Highlights

As semiconductor technology continues to advance, Static Random-Access Memory (SRAM) cells designed with minimum sizes are more susceptible to process fluctuations [1]
A yield analysis framework is developed by integrating our Spline-High Dimensional Model Representation (SP-High Dimensional Model Representation (HDMR)) model into a state-of-art importance sampling method to replace expensive transistor-level simulations
We find that the majority of variables only have weak effects on SRAM read access delay, which can be viewed as a sparsity constraint on SRAM performance modeling

Summary

INTRODUCTION

As semiconductor technology continues to advance, SRAM cells designed with minimum sizes are more susceptible to process fluctuations [1]. Variation space directly and simulates each sample to get the corresponding performance at the transistor-level It is extremely time-consuming to estimate SRAM failure rates due to the huge number of simulations, e.g. it needs over 107 simulations to get a 4-sigma yield result. A yield analysis framework is developed by integrating our SP-HDMR model into a state-of-art importance sampling method to replace expensive transistor-level simulations. It aggressively improves the yield estimation overhead compared to both the traditional MC method and the pure IS-based method. It still needs large number of expensive transistor-level simulations to converge a stable result

META-MODELING

IMPLEMENTATION DETAILS

Findings

CONCLUSION