High-Density SRAM Read Access Yield Estimation Methodology

Gidong Baek,Hanwool Jeong

doi:10.1109/access.2021.3111762

Abstract

As high-density SRAMs must be designed to ensure a substantially small failure rate, the accurate yield estimation with practically acceptable runtime of circuit simulations is highly challenging. Here, a read access yield estimation method for high-density static random access memory (SRAM) is proposed. Instead of performing SPICE runs for the entire SRAM circuit, the proposed method partitions the SRAM into three parts—the control signal generation circuit, bitcell array, and sense amplifier (SA)—that determine three key parameters: word-line to SA enable delay, bit-line voltage difference, and SA offset voltage. Subsequently, the proposed method derives the probability density of these key parameters from each of the three partitioned circuits. Here, different methods are applied to derive the probability of the key parameters, considering the respective characteristics of each circuit part and parameter. According to our experimental results, the proposed method can accelerate the yield estimation by 500– $3000\times $ , compared with the brute-force Monte Carlo simulation method, and 10– $100\times $ compared with the other state-of-art methods. In addition, the proposed method can accelerate the circuit optimization procedure accompanied by multiple circuit revisions, that is, the circuit revisions can be reflected with SPICE runs only for the revised circuit part, unlike the previous methods that require SPICE runs for the entire SRAM.

Highlights

Static random access memory (SRAM) is widely used as embedded memory in the recent system-on-chip (SoC) paradigm
EXPERIMENT RESULTS Pfail,bitcell is estimated using the proposed method discussed in the previous section and compared with the other previous yield estimation methods in terms of the accuracy and efficiency
A VT / 2 LgNfin(2Hfin + Tfin) where A VT is Pelgrom constant which is determined based on the silicon measurement results of 7nm finFET in [21], and Lg, Wg, Nfin, Hfin, and Tfin are gate length, gate width, the number of fin, fin height and fin thickness in a finFET, respectively

Summary

Introduction

Static random access memory (SRAM) is widely used as embedded memory in the recent system-on-chip (SoC) paradigm. SRAM bitcells designed nearly minimum sized transistors, making it extremely sensitive to process variations. This means that the SRAM is highly vulnerable to operation failure, and the yield of SoC is critically determined by SRAM. The read access failure that is incorrect sensing of the stored data, is one of the most critical failures in SRAM. Because the small-sized bitcell has a poor current drivability, VBL increases extremely slowly and highly limits the read access speed. In this case, VBL is positive, and DOUT becomes high.

Methods

Results

Conclusion