Back gate impact on SEU characterization of a Double SOI 4k-bit SRAM

Abstract

In this paper, heavy-ion single-event effects studies are investigated on a 0.2 μm Double silicon-on-insulator (DSOI) 4k bit Static Random Access Memory (SRAM). The back gate bias is used to adjust the single event upset (SEU) rate of the SRAM circuit. Experimental results show that applying a -5 V bias to the back gate of nMOSFETs can reduce the SEU cross section by 31 % ~ 62 %, and the SEU rate by 61 %. While applying to the back gate of both nMOSFETs and pMOSFETs a 5 V bias can increase the SEU cross section by 43 % ~ 298 %, and the SEU rate by 3 orders of magnitude. The SEU rate is calculated using OMERE software under the GEO orbit with a 3 mm aluminum shielding condition. To further analyze the cause of this phenomenon, TCAD simulation and DSOI MOSFETs test were introduced in this paper. Results show that applying a negative bias to the back gate of nMOSFETs will reduce the single particle transient (SET) and increase the threshold voltage of nMOSFETs, which makes the SRAM cell more tolerant to SEU; while applying a positive bias to the back gate of pMOSFETs will decrease the drive current of pMOSFETs, which makes the SRAM cell more sensitive to SEU.