Static Random Access Memory Circuit Research Articles

Subthreshold FinFET SRAM at 20nm Technology with Improved Stability and Lower Leakage Power

Background/Objectives: The Complementary Metal–Oxide–Semiconductor (CMOS) scaling feature was the wonderful feature which led the electronics market into in an era of miniaturization but with the fascinating feature some limitations has also been observed. Methods/Statistical analysis: CMOS technology has also given a new horizon to the memory circuits like Static Random-Access Memory (SRAMs). To overcome the limitations of scaling of the CMOS technology, Fin Field Effect Transistor (FinFET) technology has been chosen. To overcome the limitations of scaling of the CMOS technology, FinFET technology has been chosen. Like CMOS SRAMs, FinFET SRAMs have also gained popularity because of the advantages as discussed in this paper. Findings: In this paper, FinFET SRAM cells have been proposed in three different configurations for better stability and reduced leakage power in sub threshold region at 20nm technology.4 different modes of FinFET has been used to implement the SRAM. The FinFETs are classified as (i) SG-mode (ii) LP-mode and (iii) IG mode. A comprehensive analysis has been made for all the 4 types of SRAM stability which includes for Read Margin, Write Margin, Hold Margin and leakage power analysis by finding the leakage current for all the proposed circuits and has compared with the previous work and it has been found that the proposed circuits serves better in terms of stability and reduced leakage current. The cell has been implemented for sub threshold voltages ranging from 0.4V to 0.1V. The maximum Write Margin at 0.4V is 196.9mV, Read Margin is 110 mV. Application/Improvements: It has been found that from the different SRAM circuits, IG-P has the maximum Write SNM, Read SNM and hold margin while LP mode has minimum leakage current, next the IG-P mode FinFET.

ANALYSIS OF STATIC NOISE MARGIN FOR NOVEL POWER GATED SRAM

Data stability is one of the important parameter of SRAM with scaling of CMOS technology. However the move to nanometer technology not only nodes has increased, but the variability in device characteristics has also increased due to large process variations. Static random access memory (SRAM) is a popular component which is used in modern microprocessors and occupies a considerable chip area. It is useful to store the data as well as read and write operation. The performance of SRAM circuit is measured with data stability and read-write SNM (Static Noise Margin). A novel power gated SRAM cell is presented in this paper with enhanced data stability and reduced leakage power. The data becomes completely isolated form bit line during read operation in new power gated SRAM. The SNM of the new power gated cell is thereby increased by 2 times in comparison to a conventional six transistor (6T) SRAM cell. The paper also covers the comparative analysis and simulation of both SRAM cell on the basis of Read Noise Margin and Write Noise Margin. The novel power gated SRAM cell has larger read and write SNM as compared to conventional 6T SRAM cell at different technologies. All results are carried out on 45nm, 32nm and 22nm CMOS technology using HSPICE simulation tool.

Low power and robust memory circuits with asymmetrical ground gating

Multi-threshold CMOS (MTCMOS) technique is commonly used for suppressing leakage currents in idle circuits. The application of MTCMOS technique to static random access memory (SRAM) circuits is investigated in this paper. Two asymmetrically ground-gated MTCMOS SRAM circuits are presented for providing a low-leakage SLEEP mode with data retention capability. The read and hold static noise margins are increased by up to 7.24× and 2.39×, respectively, with the new asymmetrical SRAM cells as compared to conventional six-transistor (6T) SRAM cells in a 65nm CMOS technology. The overall electrical quality of a memory array is enhanced by up to 103.52× and 57.75% with the proposed asymmetrically ground-gated memory cells as compared to the conventional ground-gated 6T and eight-transistor (8T) SRAM cells, respectively. The new asymmetrical SRAM cells also exhibit enhanced tolerance to process parameter variations and lower minimum applicable power supply voltages as compared with the conventional 6T and 8T SRAM cells.

Variability-aware 7T SRAM circuit with low leakage high data stability SLEEP mode

The design of nanoscale static random access memory (SRAM) circuits becomes increasingly challenging due to the degraded data stability, weaker write ability, increased leakage power consumption, and exacerbated process parameter variations in each new CMOS technology generation. A new asymmetrically ground-gated seven-transistor (7T) SRAM circuit is proposed for providing a low leakage high data stability SLEEP mode in this paper. With the proposed asymmetrical 7T SRAM cell, the data stability is enhanced by up to 7.03x and 2.32x during read operations and idle status, respectively, as compared to the conventional six-transistor (6T) SRAM cells in a 65nm CMOS technology. A specialized write assist circuitry is proposed to facilitate the data transfer into the new 7T SRAM cells. The overall electrical quality of a 128-bit×64-bit memory array is enhanced by up to 74.44x and 13.72% with the proposed asymmetrical 7T SRAM cells as compared to conventional 6T and 8T SRAM cells, respectively. Furthermore, the new 7T SRAM cell displays higher data stability as compared to the conventional 6T SRAM cells and wider write voltage margin as compared to the conventional 8T SRAM cells under the influence of both die-to-die and within-die process parameter fluctuations.

Solution-processed carbon nanotube thin-film complementary static random access memory.

Over the past two decades, extensive research on single-walled carbon nanotubes (SWCNTs) has elucidated their many extraordinary properties, making them one of the most promising candidates for solution-processable, high-performance integrated circuits. In particular, advances in the enrichment of high-purity semiconducting SWCNTs have enabled recent circuit demonstrations including synchronous digital logic, flexible electronics and high-frequency applications. However, due to the stringent requirements of the transistors used in complementary metal-oxide-semiconductor (CMOS) logic as well as the absence of sufficiently stable and spatially homogeneous SWCNT thin-film transistors, the development of large-scale SWCNT CMOS integrated circuits has been limited in both complexity and functionality. Here, we demonstrate the stable and uniform electronic performance of complementary p-type and n-type SWCNT thin-film transistors by controlling adsorbed atmospheric dopants and incorporating robust encapsulation layers. Based on these complementary SWCNT thin-film transistors, we simulate, design and fabricate arrays of low-power static random access memory circuits, achieving large-scale integration for the first time based on solution-processed semiconductors.

Long single ZnO nanowire for logic and memory circuits: NOT, NAND, NOR gate, and SRAM

We demonstrate logic and static random access memory (SRAM) circuits using a 100 μm long and 100 nm thin single ZnO nanowire (NW), which acts as a channel of field-effect transistors (FETs) with Al2O3 dielectrics. NW FETs are thus arrayed in one dimension to consist of NOT, NAND, and NOR gate logic, and SRAM circuits. Two respective top-gate NW FETs with Au and indium-tin-oxide (ITO) were connected to form an inverter, the basic NOT gate component, since the former gate leads to an enhanced mode FET while the latter to depletion mode due to their work function difference. Our inverters showed a high voltage gain of 22 under a 5 V operational voltage, resulting in successful operation of all other devices. We thus conclude that our long single NW approach is quite promising to extend the field of nano-electronics.

New method of optimizing writing parameters in electron beam lithography systems for throughput improvement considering patterning fidelity constraints

Low-energy electron beam lithography is one of the promising next-generation lithography technology solutions for the 21-nm half-pitch node and beyond because of fewer proximity effects, higher resist sensitivity, and less substrate damage compared with high-energy electron beam lithography. To achieve high-throughput manufacturing, low-energy electron beam lithography systems with writing parameters of larger beam size, larger grid size, and lower dosage are preferred. However, electron shot noise can significantly increase critical dimension deviation and line edge roughness. Its influence on patterning prediction accuracy becomes nonnegligible. To effectively maximize throughput while meeting patterning fidelity requirements according to the International Technology Roadmap for Semiconductors, a new method is proposed in this work that utilizes a new patterning prediction algorithm to rigorously characterize the patterning variability caused by the shot noise and a mathematical optimization algorithm to determine optimal writing parameters. The new patterning prediction algorithm can achieve a proper trade-off between computational effort and patterning prediction accuracy. Effectiveness of the new method is demonstrated on a static random-access memory circuit. The corresponding electrical performance is analyzed by using a gate-slicing technique and publicly available transistor models. Numerical results show that a significant improvement in the static noise margin can be achieved.

Worst-case total dose radiation effect in deep-submicron SRAM circuits

The worst-case radiation effect in deep-submicron SRAM (static random access memory) circuits is studied through theoretical analysis and experimental validation. Detailed analysis about the radiation effect in different parts of circuitry is presented. For SRAM cells and a sense amplifier which includes flip-flop structures, their failure level against ionizing radiation will have a connection with the storage state during irradiation. They are inclined to store or read the same state as the one stored during irradiation. Worst-case test scheme for an SRAM circuit is presented, which contains a write operation that changes the storage states into the opposite ones after irradiation and then a read operation with opposite storage states. An irradiation experiment is designed for one 0.25 μm SRAM circuit which has a capacity of 1 k × 8 bits. The failure level against ionizing radiation concluded from this test scheme (150 krad(Si)) is much lower than the one from the simplest test scheme (1 Mrad(Si)). It is obvious that the failure level will be overestimated if the simplest test scheme is chosen as the test standard for SRAM circuits against ionizing radiation.

On the Variability in Planar FDSOI Technology: From MOSFETs to SRAM Cells

In this paper, an in-depth variability analysis, i.e., from the threshold voltage V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">T</sub> of metal-oxide-semiconductor field-effect-transistors (MOSFETs) to the static noise margin (SNM) of static random-access memory (SRAM) cells, is presented in fully depleted silicon-on-insulator (FDSOI) technology. The local V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">T</sub> variability σ(V) <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">T</sub> lower than A(V) <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">T</sub> = 1.4 mV · μm is demonstrated. We investigated how this good V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">T</sub> variability is reported on the SNM fluctuations σ <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">SNM</sub> at the SRAM circuit level. It is found experimentally that σ <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">SNM</sub> is correlated directly to the σ(V) <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">T</sub> of SRAM transistors without any impact of the mean SNM value. The contributions of the individual MOSFETs in the SRAM cells have been determined quantitatively by using a homemade Simulation Program with Integrated Circuit Emphasis compact model calibrated on our FDSOI electrical characteristics. The V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">T</sub> variability in n-channel MOSFETs (nMOSFETs) is more critical than that in p-channel MOSFETs for SNM fluctuations, and σ(V) <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">T</sub> in drive nMOSFETs is the key parameter to control for minimizing σ <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">SNM</sub> .

Speed and Leakage Power Trade-off in Various SRAM Circuits

The growing demand of multimedia rich applications in handled portable devices continuously driving the need for large and high speed embedded Static Random Access Memory (SRAM) to enhance the system performance. Many circuit techniques, e.g. body bias, bit charge recycling etc., have been proposed to expand design margins at low voltage operation while reducing leakage current at standby mode, but the performance is analyzed at the cost of speed and this issue is not addressed widely. Also due to continuous scaling of CMOS, the process variations also affect the performance of SRAMs. This paper presents the analysis of low leakage SRAM along with the speed factor.

An Experimental 0.8 V 256-kbit SRAM Macro with Boosted Cell Array Scheme

This work presents a low-voltage static random access memory (SRAM) technique based on a dual-boosted cell array. For each read/write cycle, the wordline and cell power node of selected SRAM cells are boosted into two different voltage levels. This technique enhances the read static noise margin to a sufficient level without an increase in cell size. It also improves the SRAM circuit speed due to an increase in the cell read-out current. A 0.18 µm CMOS 256-kbit SRAM macro is fabricated with the proposed technique, which demonstrates 0.8 V operation with 50 MHz while consuming 65 µW/MHz. It also demonstrates an 87% bit error rate reduction while operating with a 43% higher clock frequency compared with that of conventional SRAM.

High-throughput high-density mapping and spectrum analysis of transistor gate length variations in SRAM circuits

High-throughput high-density mapping of gate length variations using static random-access memory (SRAM) as electronic test structures is reported. In the experiments, direct measurements of bit-line currents revealed the individual transistor gate length variations within every memory cell. With SRAM and its fast addressing circuits we can measure CD variations with measurement time as fast as 5 /spl mu/s per data point and spatial periodicities down to 6 /spl mu/m. Layout-dependent periodic errors were found to take up 30% to 90% of the total observed error variance, depending on the spatial frequency range and specific measurement grid used. Peaks in the error spectrum were found to be related to the periodicities existing in the circuit layout. Lithography simulations were done as efforts to identify the periodic error sources. It was found that proximity effects and pattern-dependent coma effects contributed to a large percentage of the high spatial frequency errors observed. By independent optical measurements of the poly mask, it was found that the CD error contributions from the mask are very small, and are negligible when compared to the stepper-lens-induced CD errors.

Exploiting symmetry when verifying transistor-level circuits by symbolic trajectory evaluation

We describe the use of symmetry for verification of transistor-level circuits by symbolic trajectory evaluation (STE). We present a new formulation of STE which allows a succinct description of symmetry properties in circuits, Symmetries in circuits are classified as structural symmetries, arising from similarities in circuit structure, data symmetries, arising from similarities in the handling of data values, and mixed structural-data symmetries. We use graph isomorphism testing and symbolic simulation to verify the symmetries in the original circuit, Using conservative approximations, we partition a circuit to expose the symmetries in its components, and construct reduced system models which can be verified efficiently, Introducing X-drivers into switch-level circuits simplifies the task of creating conservative approximations of switch-level circuits, Our empirical results show that exploiting symmetry with conservative approximations can allow one to verify systems several orders of magnitude larger than otherwise possible. We present results of verifying static random access memory circuits with up to 1.5 Million transistors,.

A 0.8- mu m CMOS technology for high-performance ASIC memory and channelless gate array

A 0.8- mu m polycide-gate, double-layer-metal CMOS technology is described. Nominal device gate lengths down to 0.8 (+or-0.2) mu m are used for both n- and p-channel transistors. Compact isolation, 175-A gate oxide grown in dry/wet/dry ambient, shallow-junction halo-implanted lightly doped drain n and p devices, TiN contact barrier, and a planarized double-layer-metal process are all integrated and demonstrated with a 0.8- mu m full-CMOS 16K SRAM (static random-access memory) circuit. The device process integrity, design margins, performance, reliability, product yield and speed enhancement are all discussed in detail.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>