Reliability and Energy Efficiency of the Tunneling Transistor-Based 6T SRAM Cell in Sub-10 nm Domain

Abstract

The static random access memory (SRAM) has a significant impact on the overall power consumption and energy efficiency of any micro and nanoelectronics application or system. SRAM consumes a considerable amount of power in the idle state. As a consequence, the leakage power is one of the most critical metrics in SRAM designs. This brief evaluates the standby leakage power in the tunnel FET (TFET)-based 6T SRAM cell for different pull-up, pull-down, and pass-gate transistors ratios (PU: PD: PG) and compared to 10-nm FinFET-based 6T SRAM designs. It is observed that the 10-nm TFET-based SRAMs have 60.7, 65.22, and 59.7 times less standby leakage power compared to the 10-nm FinFET-based SRAMs when the PU: PD: PG ratios are 1:1:1, 1:5:2, and 2:5:2, respectively. This brief also presents an analysis of the stability and reliability of TFET-based 6T SRAM circuit with a reduced supply voltage of 500 mV. The static noise margin, which is a critical measure of SRAM stability and reliability, is determined for hold, read and write operations of the 6T TFET SRAM cell. The robustness of the optimized TFET-based 6T SRAM circuit is also evaluated at different supply voltages. Simulations were done in HSPICE and cadence tools.