SOS Technology Research Articles

Concurrent Design Analysis of High-Linearity SP10T Switch With 8.5 kV ESD Protection

This paper discusses concurrent design and analysis of the first 8.5 kV electrostatic discharge (ESD) protected single-pole ten-throw (SP10T) transmit/receive (T/R) switch for quad-band (0.85/0.9/1.8/1.9 GHz) GSM and multiple-band WCDMA smartphones. Implemented in a 0.18 <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex Notation="TeX">$\mu$</tex> </formula> m SOI CMOS, this SP10T employs a series-shunt topology for the time-division duplex (TDD) transmitting (Tx) and receiving (Rx), and frequency-division duplex (FDD) transmitting/receiving (TRx) branches to handle the high GSM transmitter power. The measured <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex Notation="TeX">$P_{-0.1\ {\rm dB}}$</tex></formula> , insertion loss and Tx-Rx isolation in the lower/upper bands are 36.4/34.2 dBm, 0.48/0.81 dB and 43/40 dB, respectively, comparable to commercial products with no/little ESD protection in high-cost SOS and GaAs technologies. Feed-forward capacitor (FFC) and AC-floating bias techniques are used to further improve the linearity. An ESD-switch co-design technique is developed that enables simultaneous whole-chip design optimization for both ESD protection and SP10T circuits.

Single-Event Transient Effect on a Self-Biased Ring-Oscillator PLL and an LC PLL Fabricated in SOS Technology

The single-event transient effect on a ring-oscillator based and an LC-tank based phased-locked loop circuits fabricated in a 0.25 μm silicon-on-sapphire technology is analyzed with circuit-level simulations followed by laser experiments. Advantages of the LC-tank based circuits in terms of single-event tolerance over the ring-oscillator based circuits are discussed.

Method for online nondestructive hardness assurance for CMOS LSI circuits realized in SOS technology

The radiation performance of digital CMOS circuits realized in SOS technology is investigated in relation to the radiation-induced charge at the silicon-sapphire interface. A nondestructive hardness-assurance method based on radiation annealing is proposed, and reasons are given why this approach should be feasible. The limits of applicability of the method are assessed.

Etching Process Simulation in MOS Nanoscale Structures

Problems of etching process, related with MOS transistors separation in LOCOS and SOS technologies were researched. Wafer of Si selection depending on crystallographic planes orientation is the main task. The etching rate along direct direction and lateral encroachment depends on crystallographic planes orientation. Wet etching is simulated with program ACES. Test photo mask with 100 nm holes for wafer etching is used for etching process simulation. The highest etching rate reached in Si with crystallographic planes orientation (110) – 23 nm/s. The biggest lateral etching belongs to substance with crystallographic planes orientation (100), 17 nm/s on both sides together in wet etching process. Ill. 11, bibl. 6 (in English; summaries in English, Russian and Lithuanian).

Dominant mechanisms of transient-radiation upset in CMOS RAM VLSI circuits realized in SOS technology

The dominant mechanisms are analyzed of transient-radiation upset in CMOS RAM VLSI circuits realized in SOS technology. Data reliability under transient irradiation is discussed in relation to photocurrents, rail-span collapse, and the circuit and layout design of memory cells. The response is simulated of SOS integrated resistors to transient radiation. Optimal parameter values are thus determined for the resistor used in the RC network of a memory cell. It is found that the data reliability of the memory circuits considered is affected by the cross coupling of memory cells sharing a read/write line. The lifetime of radiation-induced charge carriers is estimated by experiment and computer simulation.

SOS and CMOS differential micromagnetodiodes with electrically controlled sensitivity

Essentially new experimental results of two parallel-field differential micromagnetodiodes based on SOS and CMOS technologies with electrically controlled sensitivity are presented. A dramatic increase of the magnetosensitivity by introduction of discontinuous gates in SOS devices, operating in accumulation condition and by forming of additional n +–p junctions in CMOS ones working with extraction mode are achieved. It is shown that the transducer efficiency increases 4.2 and 11.9 times, respectively, in comparison to sensors without gates and collectors. At low frequencies f ≤ 1 kHz, the internal noise of two devices is of 1/ f type. Parasitic effects at f ≤ 35 kHz frequencies of alternating magnetic field are not expected.

Radial confinement in lateral power devices

The aim of this paper is to demonstrate a novel, radial confinement approach to improve the breakdown performance of a lateral power device. The key feature is that the drift region width decreases gradually from the anode to the cathode to achieve charge confinement in the radial direction. As a result, the n− drift region concentration can be increased by a factor of 7 in comparison to a conventional counterpart leading to a lower specific on-state resistance. This technique is applicable to silicon-on-insulator technologies, such as the SOI or SOS, and to high-voltage thin-film transistor technologies on glass. Experimental results from radial diodes fabricated in SOS technology show a blocking capability higher than from those of their conventional counterparts.

Integration of sol-gel derived PZT with sos technology

Abstract PZT thin films up to 3000A have been grown via a sol-gel route onto metallized sapphire substrates. Sharp X-ray peaks of perovskite indicating mixed or highly (111) oriented PZT were obtained and a link made to the thermal processing applied. Ferroelectric properties of these samples are discussed in light of development of a 4 kbit NVRAM demonstrator on SOS, which is also introduced. The relative merits of these properties along with endurance measurements are discussed with particular emphasis on the implications for complete integration with conventional SOS-based technology, in the context of non-volatile memory applications.

Influence of silicon-sapphire interface defects on SOS MESFET behavior

Silicon MESFETs in silicon-on-sapphire SOS technology were studied and a comparison was made between simulated and measured I- V characteristics of normally-off transistors. The comparisons have shown that the effective conducting-channel depth is only 40% of the actual Si film thickness. A novel simulation approach to compensate for the lack of free carriers close to the sapphire interface is described. Results from measured transistors is presented together with simulated behavior, and also a comparison between simulated and experimental complementary MESFET (CMES) inverter behavior is done. The influence of interface defects on subthreshold current is also discussed.

A 256-channel C/SUP 2/MOS LSI time-switch using shift-register pipeline multiplexer

SOS technology has been used to retain the pipeline processing speed advantage by controlling the capacitance of on-chip lines that must be long to provide 256-channel operation. Clocked CMOS (C/SUP 2/MOS) circuits have been used to avoid clock-skew problems. A 1.5-/spl mu/m C/SUP 2/MOS/SOS technology has made it possible to integrate 900 transistors into a 4.0/spl times/2.4-mm/SUP 2/ area, and to realize a 256-channel time-switch LSI, with a 15-ns typical output delay time and a 300-mW power dissipation during 25-MHz operation.

A comparison of fine-dimension silicon-on-sapphire and bulk-silicon complementary MOS devices and circuits

The fabrication of fine-dimension silicon-gate MOS devices on both silicon-on-sapphire and bulk-silicon substrates has made possible a direct comparison of the electrical characteristics of devices based on these technologies. The same CMOS test chip design was used in both cases and provided both n- and p-channel devices having gate dimensions ranging down to submicrometer levels. Extensive electrical evaluation of the resulting devices has enabled quantitative comparison of carrier mobilities, short- and narrow-channel threshold voltage shifts, punchthrough, and subthreshold characteristics for SOS and bulk-silicon technologies. The effect of epitaxial film thickness on these properties for SOS devices is also discussed. An anomalous narrow-channel threshold voltage shift effect is observed in SOS devices and explained in terms of parasitic device characteristics. The general conclusion based on the observations made is that short-and narow-channel effects in SOS devices are significantly less of a problem than in bulk silicon devices at these gate dimensions. The direct comparison of the dynamic performance of SOS and bulk CMOS circuits can be obscured, for example by differences in gate oxide thickness and threshold voltages. In this case, however, both gate oxide thickness and threshold voltages have been closely matched. This, together with the fact that the circuits were fabricated by the same processing facility using the same chip design, should increase the reliability of any comparison. The results have indicated that at 1-µm dimensions the propagation delay of SOS CMOS circuits is 60 percent lower than that of equivalent bulk-silicon CMOS circuits.

Activation Energies of Oxide Charge Recovery in SOS or SOI Structures after an Ionizing Pulse

MOS transistors in either SOS technology with oxidation temperature varations or laser-recrystallized SOI have been exposed to ionizing pulse in order to derive activation energy of oxide charge recovery. It is found a direct dependence of annealing activation energy on oxidation or on highest temperature, and on electric field. In case of SOI, substrate oxide must also be considered. Models are discussed, based on an exponential distribution of states above the valence band and/or on polaron effect.

CMOS/SOS VLSI Technology

ABSTRACTCMOS is considered as a prospective technology in the VLSI era because of its low power consumption and high driving capability. While ordinary bulk silicon CMOS devices are inferior to SOS CMOS devices in chip area, operation speed and latch-up problem due to the need for isolation wells. SOS is an inherent good partner of the CMOS circuits owing to the simple and perfect isolation. SOS technology, however, has the problem of high wafer cost. Consequently, SOS technology is best applied to high performance logic devices. Latest results of 8k-gate CMOS/SOS gate array and 16×16bit multipliers show 0.87ns 2-NAND gate delay and 27ns multiplication time, respectively, which compete with ECL devices. Application of SOS devices down to 1μm is also promising for very high speed operation. A 78ps gate delay is achieved by double solid phase epitaxy and 1μm technology. INTRO

Analysis of leakage currents in CMOS/SOS devices

Understanding the origin and mechanism of leakage currents in CMOS/SOS transistors constitutes an important step towards the advancement of SOS technology for VLSI applications. In this letter, the bias and geometrical dependence of both n- and p-channel transistors has been analysed in detail. These variations have been correlated with independent lifetime measurements, which indicate that both bulk generation and back surface inversion play important roles in controlling leakage in SOS devices.

Characterization of CMOS Devices for VLSI

CMOS bulk and SOS technologies are discussed for VLSI with emphasis on static and dynamic characteristics of two-input NAND gates. Olpthnum performance (minimum figure of merit FM= f/sub pd/P/sub d/) is obtained for a CMOS/SOS two-input NAND gate (FO = 2, C/sub L/ = 22 fF) with an electrical channel length L = 0.75 /spl mu/m, channel width W= 5.0 /spl mu/m, and oxide thickness X/sub O/ = 450 /spl Aring/with V/sub DD/ = 3.0 V, to yield t/sub pd/ = 400 ps and P/sub d/ = 250 /spl mu/W (t/sub pd/P/sub d/ = 100 fJ) at room temperature. Bulk technology performs within a factor of 2 of SOS for t/sub pd/ and P/sub d/. CMOS technologies offer subnanosecond propagation delays, similar to ECL bipolar, at the low submilliwatt power levels of CMOS. An analytical expression for t/sub pd/ describes the performance of two-input NAND gates in terms of device modeling and fabrication parameters. Such an expression provides a hierarchal modeling approach to characterize mini-cells for VLSI.

Characterization of CMOS devices for VLSI

CMOS bulk and SOS technologies are discussed for VLSI with emphasis on static and dynamic characteristics of two-input NAND gates. Optimum performance (minimum figure of merit FM = t <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">pd</inf> P <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">d</inf> ) is obtained for a CMOS/SOS two-input NAND gate (FO = 2, C <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">L</inf> = 22 fF) with an electrical channel length L = 0.75 µm, channel width W = 5.0 µm, and oxide thickness X <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">o</inf> = 450 Å with V <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">DD</inf> = 3.0 V, to yield t <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">pd</inf> = 400 ps and P <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">d</inf> = 250 µW (t <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">pd</inf> P <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">d</inf> = 100 fJ) at room temperature. Bulk technology performs within a factor of 2 of SOS for t <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">pd</inf> and P <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">d</inf> . CMOS technologies offer subnanosecond propagation delays, similar to ECL bipolar, at the low submilliwatt power levels of CMOS. An analytical expression for t <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">pd</inf> describes the performance of two-input NAND gates in terms of device modeling and fabrication parameters. Such an expression provides a hierarchial modeling approach to characterize minicells for VLSI.

I-1 performance comparison of MOSLSI built using bulk and SOS technology

I-1 performance comparison of MOSLSI built using bulk and SOS technology

A new dielectric isolation method using porous silicon

A new dielectric isolation technology is proposed. In the new structure, single crystalline Si islands are separated from the silicon substrate by oxidized porous silicon. It is based on the following characteristics of the porous silicon oxide formation: (1) p-type Si is more easily changed to porous silicon than n-type Si; (2) porous silicon is formed along the anodic reaction current flow line; (3) the change in volume of porous silicon after oxidation is relatively small; (4) thick porous silicon films (10 μm) can be obtained easily. In this method, a p-type isolated layer is obtained by proton implantation used for an n-type layer formation. Lateral p- n junctions fabricated in such isolated silicon layers show lower leakage current than those reported in SOS technology.

MP-A6 characteristics of short-channel MOS transistors fabricated using bulk and SOS technology

MP-A6 characteristics of short-channel MOS transistors fabricated using bulk and SOS technology

An integrated magnetic sensor : the silicon on sapphire Schottky magnetodiode

The Schottky magnetodiode is the combination of two basic phenomena : the magnetodiode effect in double-injecting P+ NN+ structures and the effect of the carrier density modulation on the Schottky reverse current. Our devices, realized in SOS technology, denote magnetosensitivities of about 10 V/T. We investigate the influence of the geometrical parameters, injection rate and doping level in order to improve the device sensitivity.