Characterization of CMOS Devices for VLSI

Abstract

CMOS bulk and SOS technologies are discussed for VLSI with emphasis on static and dynamic characteristics of two-input NAND gates. Olpthnum performance (minimum figure of merit FM= f/sub pd/P/sub d/) is obtained for a CMOS/SOS two-input NAND gate (FO = 2, C/sub L/ = 22 fF) with an electrical channel length L = 0.75 /spl mu/m, channel width W= 5.0 /spl mu/m, and oxide thickness X/sub O/ = 450 /spl Aring/with V/sub DD/ = 3.0 V, to yield t/sub pd/ = 400 ps and P/sub d/ = 250 /spl mu/W (t/sub pd/P/sub d/ = 100 fJ) at room temperature. Bulk technology performs within a factor of 2 of SOS for t/sub pd/ and P/sub d/. CMOS technologies offer subnanosecond propagation delays, similar to ECL bipolar, at the low submilliwatt power levels of CMOS. An analytical expression for t/sub pd/ describes the performance of two-input NAND gates in terms of device modeling and fabrication parameters. Such an expression provides a hierarchal modeling approach to characterize mini-cells for VLSI.