ESD issues in advanced CMOS bulk and FinFET technologies: Processing, protection devices and circuit strategies

Abstract

The ESD performance of several CMOS bulk and SOI technologies is reviewed. The ESD area-efficiency of FinFETs is put in relation to bulk and SOI. CMOS bulk technologies have improved over the past generations owing to the possibility of reduced ESD layout dimensions. While having observed It2 values of less than 2 mA/μm 2 in 130 nm technology, we are able to obtain almost 4 mA/μm 2 in 45 nm. Downscaling will shift the challenge for a robust ESD design from the ESD protection device in the IO cell to the metal routing and voltage clamping in the supply tree. This will increase cost and effort for ESD protection of modern IC’s in spite of improvement in It2. For FinFET technologies, the influence of device layout, electrical operation modes and processing is discussed. The initially extremely low ESD values of FinFETs have been strongly improved by overall process maturity and added process features. The ESD levels of FinFET technologies are now scalable up to the levels compliant with full IC design constraints. While the area-performance is still about two times lower than in bulk CMOS, it is much better than anticipated earlier. In light of the challenges ahead for technology and circuit applications, the impact on ESD protection strategies is studied. Classical protection approaches are critically examined regarding the latest technology developments and new requirements for IO interface circuits. A switch from bulk to FinFET technology is still regarded as a major disruption for product architecture and thus ESD.