Dominant mechanisms of transient-radiation upset in CMOS RAM VLSI circuits realized in SOS technology

Abstract

The dominant mechanisms are analyzed of transient-radiation upset in CMOS RAM VLSI circuits realized in SOS technology. Data reliability under transient irradiation is discussed in relation to photocurrents, rail-span collapse, and the circuit and layout design of memory cells. The response is simulated of SOS integrated resistors to transient radiation. Optimal parameter values are thus determined for the resistor used in the RC network of a memory cell. It is found that the data reliability of the memory circuits considered is affected by the cross coupling of memory cells sharing a read/write line. The lifetime of radiation-induced charge carriers is estimated by experiment and computer simulation.