Silicon-on-insulator Technology Research Articles

Sub-pixel response of double-SOI pixel sensors for X-ray astronomy

We have been developing the X-ray silicon-on-insulator (SOI) pixel sensor called XRPIX for future astrophysical satellites. XRPIX is a monolithic active pixel sensor consisting of a high-resistivity Si sensor, thin SiO2 insulator, and CMOS pixel circuits that utilize SOI technology. Since XRPIX is capable of event-driven readouts, it can achieve high timing resolution greater than ∼10 μs, which enables low background observation by adopting the anti-coincidence technique. One of the major issues in the development of XRPIX is the electrical interference between the sensor layer and circuit layer, which causes nonuniform detection efficiency at the pixel boundaries. In order to reduce the interference, we introduce a Double-SOI (D-SOI) structure, in which a thin Si layer (middle Si) is added to the insulator layer of the SOI structure. In this structure, the middle Si layer works as an electrical shield to decouple the sensor layer and circuit layer. We measured the detector response of the XRPIX with D-SOI structure at KEK. We irradiated the X-ray beam collimated with 4 μmϕ pinhole, and scanned the device with 6 μm pitch, which is 1/6 of the pixel size. In this paper, we present the improvement in the uniformity of the detection efficiency in D-SOI sensors, and discuss the detailed X-ray response and its physical origins.

(Invited) SOI Technologies for RF and Millimeter Wave Applications

Silicon-on-Insulator (SOI) technology has taken the radio-frequency (RF) world by storm in the past decade. By offering high performance at low cost it has steadily displaced Gallium-Arsenide (GaAs) and Silicon-on-Sapphire (SOS) technologies to become the mainstream technology for implementing the RF switch banks in mobile applications. Indeed, in 2008 RF SOI accounted for less than 10% of switching modules in handsets, and today virtually 100% of all modern day smartphones include RF switches implemented in Partially Depleted SOI (PD SOI) on engineered and optimized trap-rich (TR) silicon based substrates. The huge success of current PD SOI (130 nm) in today’s RF market is due to significant technological improvements. First, the analog and high-frequency characteristics of the front-end of line (FEOL) active devices, i.e. advances at the transistor level, are presented, and second, the quality of the back-end of line (BEOL) process is reviewed. The BEOL encompasses the metals, dielectric layers and semiconductor substrate of the manufacturing process. Substantial losses arise in silicon substrates at RF frequencies due to the conductive nature of silicon, and simply reducing the nominal doping of the handle wafer is insufficient, as a parasitic conduction channel is induced by (even low-level) parasitic charged defects present at all silicon/insulator interface. This effect -and ways to counter it- are described in depth as it is responsible for large amounts of RF losses, parasitic coupling and high levels of non-linear signal distortion. In terms of CMOS FEOL, the RF characteristics of SOI devices are compared with those of other high-frequency technologies. It is shown that though SOI devices provide attractive RF performances, these alone do not account for SOI’s dominance in the silicon RF market (over technologies such as planar bulk or FinFETs). Indeed, on top of boasting high figures of merit (FoM) for RF applications, SOI technology owes its success to a unique compatibility with a passivation layer rich in traps that disables the aforementioned parasitic conduction channel below the buried oxide (BOX). The so called “trap-rich” substrates, that are composed of a high-defect polysilicon layer between the BOX and the high-resistivity silicon handle substrate, are virtually lossless and highly linear and are truly optimized for RF ICs. A variety of essential RF passive elements (inductors, transmission lines, filters, antennas, etc.) are presented that benefit strongly from trap-rich silicon-substrate’s properties, along with its beneficial impact on the key RF switching modules. The future trends of SOI are then addressed. A summary is made on the progress of the most advanced PD SOI nodes (65 and 45 nm) as well as the ultra-advanced Fully Depleted SOI (FD SOI) nodes (22 and 28 nm) that are demonstrating their potential for all kinds of RF and millimeter wave front-end circuit modules, such as low-noise amplifiers (LNAs), voltage controlled oscillators (VCOs), mixers, etc. From these results SOI is expected to be a big contender as a technological platform to enable mass production of 5G and IoT devices and products in the very near future. Finally, compatibility issues between advances FD SOI nodes and the trap-rich layer are discussed, and alternative silicon-based substrate solutions to overcome the problematic parasitic conduction channel are presented, such as porosification of the silicon handle, deep trap implantations, and smart PN doping patterns to fight against the unwanted conductive channel that degrades substrate RF performance, the latter technique being compatible with not only SOI but also with planar bulk technology.

(Invited) Application of Three Dimensional Chip Stacking Technology for Fully Depleted Silicon-on-Insulator Quantum Beam Imager

Requirements of a quantum beam imager such as a vertex detector in high energy physics experiment are intelligent functions which are realized by embedding memories of quantum beam hit-position, hit-charge, and hit-timing in a pixel with keeping small pixel size to achieve high spatial resolution. To satisfy the requirements, circuit layer stacking on a sensor, i.e., three dimensional (3D) technology, has been widely studied and proposed. The Silicon-on-Insulator (SOI) sensor is one of the 3D sensors because the circuits in the top silicon layer is on the sensors of the bottom silicon substrate. The circuits and sensors are electrically connected by submicron W filled vias through the buried oxide (BOX), which are called as through BOX vias (TBV). Thus, the SOI sensor has extremely higher fill factor than the bulk-CMOS sensor. In order to achieve more intelligent functions in the pixel, however, the pixel size by using the simple SOI technology is large to get the required spatial resolution. Therefore, multiple circuit layer formation by chip stacking technology is adopted. In this chip stacking, a fine pitch micro-bump technology with two-tile face-to-face stacking is employed because of the simplest 3D structure. The target of micro bump diameter and spacing are 2.5 μm and 5 μm, respectively. The SOI 3D chip stacking process is starting with the base chips which are fabricated by an 8 inch 0.2 μm fully depleted SOI pixel sensor process with five metal layers. After the metal 5 etching, an oxide film is deposited and planarized by chemical mechanical polishing (CMP). W-filled vias to a under bump metal is formed at bump formation areas. After the under bump metal deposition and patterning, metal bumps are formed. Then, two chips which are lower and upper chips are aligned and bonded face-to-face at 200℃ followed by adhesive injection. To make bonding pads on the upper chip, the upper chip handle silicon is etched until exposing the BOX and TBV by wet solution. TBV can easily connect between circuits in the upper chip and the bonding pad metal without any through silicon via (TSV) process. This is the most superior point to use the FD-SOI pixel sensor in 3D structure. The TBV size is around 0.3 μm which is much smaller than a conventional TSV whose size is around 5 μm by using the most advanced technology. In addition, this TBV can be used as interconnections between multiple chips without any TSV. Finally, bonding pad and passivation formation are done. For micro bump formation, a gold bump was utilized because the gold is oxidation-resistant metal. The micro gold bump was fabricated by two methods. One is a cone shaped gold bump manufactured by a gold nanoparticle deposition with a photoresist lift-off technique [1]. The cone shaped gold bump with 2.5 μm in diameter and 2.5 μm in height are successfully formed on the under bump metal layer. Because of the nanoparticle deposition, the gold bump is easier to deform by the bonding. Thus, the collapsibility allows low stress to the die and high reliable junctions. It is also confirmed that the bump resistance is approximately 0.25 Ω/bump from daisy chain measurement. The other is a gold cylindrical bump using a combination of inverse-tapered photoresist and low incident angle sputtering [2]. Because of narrowing at the top, lower pressure to collapse between the bumps is required than the gold cone bumps. This may also improve bump yield and reliability. 0.37 Ω/bump of the bump resistance is obtained by the gold cylindrical bumps. Using the FD-SOI 3D chip stacking technology with the cylindrical bump, the pixel sensor designed for the International Linear Collider (ILC) vertex detector called SOFIST was fabricated and the chip photo is shown in the figure. In SOFIST, hit-position, hit-charge, and hit-time memories are embedded in each pixel by the 3D micro bump bonding with 20 mm pixel size. Owing to the removal of the handle silicon of the upper chip, the patterns of the lower chip can be seen through the upper chip oxide. The green patterns close to bonding pads are backsides of silicon layer in the upper chip. As shown in the figure, our 3D process technology is successfully introduced in FD-SOI quantum beam imager.

Digital Performance of OCTO Layout Style on SOI MOSFET at High Temperature Environment

This present paper performs an experimental comparative study of the main digital parameters and figures of merit of the octagonal layout style for the planar Silicon-On-Insulator (SOI) Metal-Oxide-Semiconductor (MOS) Field Effect Transistors (MOSFET), named OCTO SOI MOSFETs (OSM) in comparison with the typical rectangular one at high temperature environments. The devices were manufactured with the 1 mm SOI (CMOS) technology. The results demonstrate that the OSM is capable of keeping active the Longitudinal Corner Effect (LCE), the PArallel Connection of MOSFETs with Different Channel Lengths Effect (PAMDLE) and the Deactivate the Parasitic MOSFETs of the Bird’s Beak Regions Effect (DEPAMBBRE) at high temperature conditions. Therefore, the OSM is able to continue to have a better electrical performance than the one found in the rectangular SOI MOSFET (RSM) counterparts, regarding the same gate areas and bias conditions. To illustrate, its on-state drain current (ION) and off-state drain current (IOFF) are respectively 186% higher and 64% smaller in relation to its RSM counterparts at high temperature conditions.

Characterization of SOI technology based MEMS differential capacitive accelerometer and its estimation of resolution by near vertical tilt angle measurements

This paper discusses the evaluation and testing of MEMS capacitive accelerometer (z-axis sensitive) fabricated using silicon-on-insulator (SOI) wafer. The accelerometer structure consists of highly conductive (p-type, resistivity: 0.001 Ω-cm) silicon proof mass (1000 μm × 1000 μm × 30 μm) suspended by four crab-like L-shaped beams (1150 μm × 30 μm × 30 μm) over Pyrex (7740) glass cavity (5 μm depth). Rest capacitance of the accelerometer structure is found to be ~ 2.1–2.25 pF range. Qualified accelerometer chips are packaged and sealed in lead less ceramic (LCC) package along with capacitive readout circuitry chip. Packaged accelerometer showed a scale factor sensitivity of ~ 47 mV/g in − 17–42 g acceleration range with 3% non-linearity. Corresponding cross-axis sensitivity also measured (2%) in full-scale range. Frequency response of the accelerometer showed a 3 dB bandwidth of 380 Hz. Resolution of the accelerometer is measured by an innovative technique involving inclinometer. Here, the device output is recorded at near vertical mounting tilt angle (θ ~ 90°) of inclinometer. Present accelerometer output can be resolved at the inclinometer measurement at 90° (output: 2.42662 V) and 89° (output: 2.42780 V) which corresponds to an acceleration resolution of ~ 17 mg.

Design of a 2 × 4 Hybrid MMI-MZI Configuration with MMI Phase-Shifters.

This paper reports design of a 2 × 4 hybrid multimode interferometer-Mach-zehnder interferometer (MMI-MZI) configuration consiting of compact thermo-optical switches on the silicon-on-insulator (SOI) platform. The device consists of two identical MMI slab waveguides as power splitters and couplers that are connected with two identical MMI-based phase shifters, and linear tapers at both ends of the MMIs to minimize the power coupling loss. A thin Al pad is used as a heating element and a trench is created around this pad to prevent heat from spreading, and to minimize loss. The calculated average thermo-optical switching power consumption, excess loss, and power imbalance are 1.4 mW, 0.9 dB, and 0.1 dB, respectively. The overall footprint of the device is 6 × 304 . The new heating method has advantages of compact size, ease of fabrication on SOI platform with the current CMOS technology, and offers low excess loss and power consumption as demanded by devices based on SOI technology. The device can act as two independent optical switches in one device.

Compact Model for Tunnel Diode Body Contact SOI n-MOSFETs

A compact model for tunnel diode body contact (TDBC) silicon-on-insulator (SOI) n-MOSFETs was developed in this paper. The compact model is implemented in Verilog-A to simulate the dc and radio frequency (RF) performance of a TDBC SOI MOSFET. The TDBC SOI MOSFETs are successfully fabricated and are used to measure important transistor electrical parameters. The investigation results reveal that TDBC structure suppresses floating body effects (FBEs) as well as T-gate body (TB) contact structure and shows significant improvement in RF performance without introducing additional parasitic capacitances compared with the TB device. Kink phenomena and an abnormal subthreshold swing originating from FBEs are sufficiently suppressed. It is demonstrated that the TDBC SOI MOSFETs provide a promising concept for digital, analog, and RF applications. The outputs from this analytic model are in fair agreement with the TDBC experimental data, which validates the effectiveness and robustness of the compact model for TDBC SOI technology. Finally, good accuracy ensures that the proposed model is applicable for the implementation in circuit simulation tools.

Temperature dependence of single-event transient response in devices with selective-buried-oxide structure

The silicon-on-insulator (SOI) device has been found to possess low leakage current and high operation speed due to reduced internal capacitances. The sensitive volume for charge collection in SOI device is smaller than that in bulk-silicon device, which improves the ability of SOI devices to resist single-event effect (SEE). In spite of these benefits, the SOI device has certain undesirable effects such as the kink effect. To mitigate the kink effect, selective-buried-oxide (SELBOX) SOI structure has been introduced. Space-borne electronic circuits based on SOI technology recently have been used in high radiation and extreme temperature environments. However, temperature affects internal carrier transport process and impact ionization process, which makes single-event transient (SET) pulse widths increased. Most of previous researches regarding temperature dependence of SEE were for SOI floating-body devices. But the influence of operating temperature on SEE of SELBOX SOI devices are yet unclear. In this paper, an SOI floating-body device and a SELBOX SOI device under 90 nm process are established by three-dimensional device simulation, and then temperature dependence of SET response in partially depleted SOI inverter chains is studied by a mixed-mode approach over a temperature range from 200 K to 450 K. Simulation results show that the N-type SELBOX SOI device has a better ability to resist SEE than the floating-body device, while the P-type SELBOX SOI device has the same ability to resist SEE at high linear energy transfer value as the floating-body device. And temperature dependence analysis of charge collection indicates that there is only drift-diffusion process in the N-type SELBOX SOI device. The amount of charge collection in the N-type SELBOX SOI device almost does not change with the increase of temperature. In addition, both the P-type SELBOX SOI device and the P-type floating-body device have a bipolar amplification process. With the increase of temperature, the bipolar amplification process in the substrate turns more serious. However, it suppresses the bipolar amplification process of the source because of SELBOX structure, so that the amount of charge collection is reduced in the drain significantly. According to our simulation results, compared with the floating-body device, the SELBOX SOI device can very well suppress the influence of temperature on SET pulse.

Resistance-Based Modeling for Soft Errors in SOI SRAMs Caused by Radiation-Induced Potential Perturbation Under the BOX

Silicon-on-insulator (SOI) technology has been considered capable of developing devices with high tolerance against soft errors. In addition, with a thin buried oxide (BOX) layer, reduction in power consumption can be further achieved by applying a back bias from under the BOX, which is one of SOI technology’s many advantages and is appealing to Internet-of-Things and space applications. Recently, it was found during a heavy ion experiment that a static random access memory fabricated with a thin-BOX SOI technology exhibited a 100-fold soft error sensitivity when it received a back-bias. This was due to long line-type formation of multiple cell upsets (MCUs) caused by radiation-induced potential perturbation under the BOX. In this paper, a resistance-based model is developed for the evaluation of potential perturbation, predicting the device soft error sensitivity. The predictions made are verified by simulation. The model also provides an explanation to why the line-type MCU only occurs in a certain radiation environment and an optimization method to reduce the potential perturbation.

A 0.1% THD, 1-M<inline-formula> <tex-math notation="LaTeX">$\Omega$ </tex-math> </inline-formula> to 1-G<inline-formula> <tex-math notation="LaTeX">$\Omega$ </tex-math> </inline-formula> Tunable, Temperature-Compensated Transimpedance Amplifier Using a Multi-Element Pseudo-Resistor

In this paper, a transimpedance amplifier (TIA) is presented that utilizes a modified pseudo-resistor (PR) with improved robustness against temperature and process variations, enhanced linearity, and reduced parasitics. Using a biasing scheme named pseudo current mirror, the conventional dependence on absolute process parameters is reduced to a dependence on matching of alike devices. The linearity and noise performance as well as the immunity against process variations of the presented TIA are improved by the series connection of multiple PR elements. Moreover, it is shown how implementing the design in a silicon-on-insulator (SOI) technology reduces critical parasitics, which in turn enables the use of the multi-element PR in high-speed, high-gain, and low-distortion TIAs. A prototype realization in a 180-nm CMOS SOI technology achieves a tunability in transimpedance of three orders of magnitude from ${1}~{\mathrm {G}\Omega }$ down to ${1}~{\mathrm {M}\Omega }$ with corresponding bandwidths from ${8}~{\mathrm {kHz}}$ to 2 MHz. By design, the contribution of shot noise is rendered negligible and the white noise floor of the prototype realization approaches the theoretical thermal noise limit, e.g., ${5.5}~{\mathrm {fA}/\sqrt {\mathrm {Hz}}}$ for a transimpedance of ${1}~{\mathrm {G}\Omega }$ and ${140}~{\mathrm {fA}/\sqrt {\mathrm {Hz}}}$ for ${1}~{\mathrm {M}\Omega }$ . Total harmonic distortion values of less than 0.1% are achieved for an input amplitude of ${300}\,\,{\mathrm {pA}_{\mathrm {p{-}p}}}$ for ${1}~{\mathrm {G}\Omega }$ , ${4.0}\,\,{\mathrm {nA}_{\mathrm {p{-}p}}}$ for ${100}~{\mathrm {M}\Omega }$ , and ${40}\,\,{\mathrm {nA}_{\mathrm {p{-}p}}}$ for ${10}~{\mathrm {M}\Omega }$ , and less than 1% is achieved for an input amplitude of ${550}\,\,{\mathrm {nA}_{\mathrm {p{-}p}}}$ for ${1}~{\mathrm {M}\Omega }$ . The presented TIA consumes an area of 0.07 mm2 and dissipates a power of 9.3 mW for the opamp and a maximum power of 0.2 mW for the PR from a 1.8-V supply.

Performance Enhancement of FinFET Devices with Gate-Stack (GS) High-K Dielectrics for Nanoscale Applications

The Fin shaped Field Effect Transistors (FinFETs), are the front runner of the current sub-nanometer technology node. The semiconductor industry adopts it in high-performance (HP) and low-power (LP) applications due to greater electrostatic control and better scalability. This paper explores the numerically simulation based comparison of bulk and silicon-on-insulator (SOI) technology double gate (DG), triple gate (TG) FinFETs. The essential processing steps required to create the GS high-k dielectric bulk and SOI FinFETs are demonstrated. The electrical performance parameters of the device such as Ion/Ioff ratio, subthreshold swing (SS), and drain induced barrier lowering (DIBL) are extracted. Based on the three-dimensional (3D) ATLASTM simulation results, TG FinFET shows an ameliorated performance over DG in bulk and SOI technology as well. In order to control the short channel effects (SCEs), gate-stack (GS) high-k dielectrics are introduced with fixed thickness interfacial-layer (IL) and high-k dielectric material in between the gate material and semiconductor. The GS high-k dielectrics suppress the SCEs to large extent in both devices and technologies. The GS SOI FinFETs demonstrates the improved performance over the bulk counterpart and TG FinFET is the best among them. Further, the similar kind of investigation has been carried out for Tfin variations. These devices reveal the excellent control of SCEs when the fin is narrow. The ratio of SOI and bulk TG FinFET Ion/Ioff ratio with Tfin variations provide evidence that, the SOI based devices are competent for HP and LP applications.

In-field and out-of-file application in 12C ion therapy using fully 3D silicon microdosimeters

This paper presents recent development of Silicon on Insulator (SOI) detectors for microdosimetry at the Centre for Medical Radiation Physics (CMRP) at the University of Wollongong. A new CMRP SOI microdosimeter design, the 3D mushroom microdosimeter is presented. Modification of SOI design and changes to the fabrication processes have led to improved definition of the microscopic sensitive volumes (SV), and thus to better modelling of the deposition of ionizing energy in a biological cell. The electrical and charge collection properties of the devices have been presented in previous works. In this study, the response of the microdosimeters in monoenergetic and spread out Bragg peak therapeutic 12C ion beam at Heavy Ion Medical Accelerator in Chiba (HIMAC, Japan) are presented. Derived relative biological effectiveness (RBE) in 12C ion radiation therapy matches the tissue equivalent proportional counter (TEPC) well, along with outstanding spatial resolution. The use of SOI technology in experimental microdosimetry offers simplicity (no gas system or HV supply), high spatial resolution, low cost, high count rates capabilities for beam characterisation and quality assurance (QA) in charged particle therapy.

Body Effects on the Tuning RF Performance of PD SOI Technology Using Four-Port Network

For partially depleted (PD) silicon-on-insulator (SOI) technology, body contact technology, such as T-gate (TB) body contact, is often used to suppress the floating body effect for analog or radio frequency (RF) circuits. RF performance is usually measured using a two-port network with body node connected to source node, thereby limiting the potential applications of PD SOI technology. In this letter, a four-port network structure was used for TB SOI MOSFET to evaluate the influence of the body potential on the RF performance. The gate to source and body capacitance were also extracted, individually. It was found that TB device can have an 89% improvement in the cut-off frequency ( ${f}_{T}$ ) by tuning the body voltage to 0.5 V when the device was operated at gate voltage equals to 0.4 V and drain voltage equals to 0.3 V. Power dissipation reduction was also observed with forward body bias and lower drain voltage. The results indicate that four-port network structure has potential in RF modeling for PD SOI technology that could facilitate integrating the PD SOI process into low power applications.

Mechanisms of atmospheric neutron-induced single event upsets in nanometric SOI and bulk SRAM devices based on experiment-verified simulation tool**Project supported by the National Natural Science Foundation of China (Grant No. 11505033), the Science and Technology Research Project of Guangdong Province, China (Grant Nos. 2015B090901048 and 2017B090901068), and the Science and Technology Plan Project of Guangzhou, China (Grant No. 201707010186).

In this paper, a simulation tool named the neutron-induced single event effect predictive platform (NSEEP2) is proposed to reveal the mechanism of atmospheric neutron-induced single event effect (SEE) in an electronic device, based on heavy-ion data and Monte-Carlo neutron transport simulation. The detailed metallization architecture and sensitive volume topology of a nanometric static random access memory (SRAM) device can be considered to calculate the real-time soft error rate (RTSER) in the applied environment accurately. The validity of this tool is verified by real-time experimental results. In addition, based on the NSEEP2, RTSERs of 90 nm–32 nm silicon on insulator (SOI) and bulk SRAM device under various ambient conditions are predicted and analyzed to evaluate the neutron SEE sensitivity and reveal the underlying mechanism. It is found that as the feature size shrinks, the change trends of neutron SEE sensitivity of bulk and SOI technologies are opposite, which can be attributed to the different MBU performances. The RTSER of bulk technology is always 2.8–64 times higher than that of SOI technology, depending on the technology node, solar activity, and flight height.

The Impact of Charge Collection Volume and Parasitic Capacitance on SEUs in SOI- and Bulk-FinFET D Flip-Flops

Measured single-event (SE) heavy-ion data for comparable silicon on insulator (SOI) and bulk silicon FinFET D flip-flop (DFF) designs demonstrate a notably greater difference between the SOI and bulk responses, which has commonly been observed. Data show greater than $30\times $ in SE upset (SEU) LET threshold and 3 orders of magnitude decrease in saturated SE cross section for SOI FinFETs when compared to bulk FinFETs. The difference in SEU threshold is shown to be due to the saturation of SE transient (SET) pulsewidths at values that are comparable to feedback-loop delays of DFF design in the SOI technology. The feedback-loop delays in FinFET technologies are significantly impacted by the inherent parasitic capacitance. For the bulk technology, SET pulsewidths do not saturate due to charge collection from the substrate region.

Estimation of the Single-Event Upset Sensitivity of Advanced SOI SRAMs

The single-event upset (SEU) sensitivity of ultra-thin silicon on insulator (SOI), SOI FinFET, and NanoWireFET static random access memories (SRAMs) is investigated using a straightforward multiple-scale approach based on open source and commercial codes. Both Monte-Carlo and technology computer aided design (TCAD) tools are used to estimate the SEU cross section of innovative technologies. Heavy-ion experiments performed on transistors are used to validate TCAD models and 3-D device structures. TCAD simulations are then performed on 3-D SRAM cells to calculate the upset threshold for each technology. It is used as upset criterion in Monte-Carlo simulations of deposited energy in silicon microvolumes to estimate the SEU cross section of innovative SOI technologies. Finally, multiple-bit upsets are addressed to draw trends on the sensitivity of such highly scaled technologies to multiple events.

Zero-group-velocity acoustic waveguides for high-frequency resonators

The propagation of the Lamb-like modes along a silicon-on-insulator (SOI)/AlN thin supported structure was simulated in order to exploit the intrinsic zero group velocity (ZGV) features to design electroacoustic resonators that do not require metal strip gratings or suspended edges to confine the acoustic energy. The ZGV resonant conditions in the SOI/AlN composite plate, i.e. the frequencies where the mode group velocity vanishes while the phase velocity remains finite, were investigated in the frequency range from few hundreds of MHz up to 1900 MHz. Some ZGV points were found that show up mostly in low-order modes. The thermal behaviour of these points was studied in the −30 to 220 °C temperature range and the temperature coefficients of the ZGV resonant frequencies (TCF) were estimated. The behaviour of the ZGV resonators operating as gas sensors was studied under the hypothesis that the surface of the device is covered with a thin polyisobutylene (PIB) film able to selectively adsorb dichloromethane (CH2Cl2), trichloromethane (CHCl3), carbontetrachloride (CCl4), tetrachloroethylene (C2Cl4), and trichloroethylene (C2HCl3), at atmospheric pressure and room temperature. The sensor sensitivity to gas concentration in air was simulated for the first four ZGV points of the inhomogeneous plate. The feasibility of high-frequency, low TCF electroacoustic micro-resonator based on SOI and piezoelectric thin film technology was demonstrated by the present simulation study.

Advanced Silicon-on-Insulator: Crystalline Silicon on Atomic Layer Deposited Beryllium Oxide

Silicon-on-insulator (SOI) technology improves the performance of devices by reducing parasitic capacitance. Devices based on SOI or silicon-on-sapphire technology are primarily used in high-performance radio frequency (RF) and radiation sensitive applications as well as for reducing the short channel effects in microelectronic devices. Despite their advantages, the high substrate cost and overheating problems associated with complexities in substrate fabrication as well as the low thermal conductivity of silicon oxide prevent broad applications of this technology. To overcome these challenges, we describe a new approach of using beryllium oxide (BeO). The use of atomic layer deposition (ALD) for producing this material results in lowering the SOI wafer production cost. Furthermore, the use of BeO exhibiting a high thermal conductivity might minimize the self-heating issues. We show that crystalline Si can be grown on ALD BeO and the resultant devices exhibit potential for use in advanced SOI technology applications.

An Investigation of High-Temperature (to 300 °C) Safe-Operating-Area in a High-Voltage Complementary SiGe on SOI Technology

Safe-operating-area (SOA) in a high-voltage complementary silicon–germanium (SiGe) (= n-p-n + p-n-p) on silicon-on-insulator (SOI) technology is investigated from 24 °C to 300 °C. Three key reliability degradation regions are identified, including: 1) high-current; 2) mixed-mode; and 3) high-power. The degradation mechanisms, which are operative, including Auger damage, mixed-mode damage, and electrothermal runaway as well as their temperature dependences are identified. Mixed-mode damage exhibits a strong negative temperature coefficient for both n-p-n and p-n-p SiGe heterojunction bipolar transistors (HBTs) up to 300 °C, which leads to an increase in the SOA from a high-voltage perspective. Electrothermal boundaries are also explored by finding ${J}_{C,{\textsf {crit}}}$ and ${V}_{{\textsf {CB}},{\textsf {crit}}}$ across the ${J}_{C}$ – ${V}_{\textsf {CB}}$ plane up to 300 °C. Both n-p-n and p-n-p SiGe HBTs show an increase in the SOA for the electrothermal boundary as temperature increases. High-current-induced damage, on the other hand, exhibits a positive temperature coefficient, which implies that high current drive should carefully be considered when using SiGe HBT circuits operated in a high-temperature environment. However, at very high temperatures (>200°C), the high current damage processes show annealing properties, which implies that at sufficiently high temperatures, annealing can dominate over Auger damage and potentially extend the SOA of the technology.

Design of Temperature-Aware Low-Voltage 8T SRAM in SOI Technology for High-Temperature Operation (25 %C–300 %C)

A temperature-aware low-voltage 8T static random access memory (SRAM) for high-temperature operations is presented. A dedicated read port with virtual ground and optimal body bias improves sensing margin under very high temperature (up to 300 °C). Bitline offset voltage for data “0” caused by the virtual ground scheme is also compensated by a replica bitline. The independent body bias control feature of the employed silicon-on-insulator (SOI) technology allows the write margin to be enhanced significantly without using any write-assist circuitry. Test chips were fabricated in a 1- $\mu \text{m}$ SOI technology with tungsten interconnect for reliability at high temperature and lesser process variation. Measurement results demonstrate that the proposed SRAM operates successfully up to 300 °C with the supply voltage range of 2–5 V. At the minimum performance variation point ( $V_{\mathrm{ DD}} = 2.5$ V), the SRAM consumes 1.48 mW and shows the access time of 156 ns and the maximum clock frequency of 14.38 MHz at 300 °C.