Estimation of the Single-Event Upset Sensitivity of Advanced SOI SRAMs

Abstract

The single-event upset (SEU) sensitivity of ultra-thin silicon on insulator (SOI), SOI FinFET, and NanoWireFET static random access memories (SRAMs) is investigated using a straightforward multiple-scale approach based on open source and commercial codes. Both Monte-Carlo and technology computer aided design (TCAD) tools are used to estimate the SEU cross section of innovative technologies. Heavy-ion experiments performed on transistors are used to validate TCAD models and 3-D device structures. TCAD simulations are then performed on 3-D SRAM cells to calculate the upset threshold for each technology. It is used as upset criterion in Monte-Carlo simulations of deposited energy in silicon microvolumes to estimate the SEU cross section of innovative SOI technologies. Finally, multiple-bit upsets are addressed to draw trends on the sensitivity of such highly scaled technologies to multiple events.