Abstract
Silicon-on-insulator (SOI) technology has been considered capable of developing devices with high tolerance against soft errors. In addition, with a thin buried oxide (BOX) layer, reduction in power consumption can be further achieved by applying a back bias from under the BOX, which is one of SOI technology’s many advantages and is appealing to Internet-of-Things and space applications. Recently, it was found during a heavy ion experiment that a static random access memory fabricated with a thin-BOX SOI technology exhibited a 100-fold soft error sensitivity when it received a back-bias. This was due to long line-type formation of multiple cell upsets (MCUs) caused by radiation-induced potential perturbation under the BOX. In this paper, a resistance-based model is developed for the evaluation of potential perturbation, predicting the device soft error sensitivity. The predictions made are verified by simulation. The model also provides an explanation to why the line-type MCU only occurs in a certain radiation environment and an optimization method to reduce the potential perturbation.
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