Power Supply Rejection Research Articles

A 0.6 V voltage reference circuit with 57 ppm/°C temperature coefficient, 73 KΩ output impedance and 0.080%/V line sensitivity for energy efficient applications

In this paper, a voltage reference circuit generating 0.6 V developed in the Semiconductor Laboratory (SCL) 0.18 μm standard CMOS technology has been presented. It is based on the principle of Beta multiplier circuit. Operating under a supply voltage of 1.8V, the proposed reference accomplishes a line sensitivity as low as 0.080%/V across a voltage range of 1.8 V to 3.5 V. In addition to a low line sensitivity, it achieves a low temperature coefficient of 57 ppm/ °C over the temperature range of −40 °C to +85 °C. The circuit furnishes a power supply rejection ratio (PSRR) of −75.72 dB. The improved load regulation feature allows the circuit to drive loads as low as 73 KΩ with minimum variation. A reliable nature of the circuit has been observed on examining the response for different process corners and variations.

Low quiescent current LDO with FVF-based PSRR enhanced circuit for EEG recording wearable devices

This paper presents a low quiescent current low-dropout regulator (LDO) with an auxiliary amplifier, flipped voltage follower (FVF)-based power supply rejection ratio enhanced circuit (FBPEC) for electroencephalogram (EEG) recording devices. The FBPEC comprises a FVF filter, current mirror, and common-source amplifier. The FBPEC exploits the characteristics of FVF filter to reduce the current consumption and increase the gain at specific frequencies. The small-signal equivalent circuit reveals the dominant pole of the FBPEC, which is affected by the output impedance and load capacitance of the common-source amplifier. The proposed LDO is designed using a 0.18 μm CMOS process and has improved power supply rejection ratio (PSRR) up to 18 dB at frequencies above 10 kHz compared to the general LDO. The proposed LDO has a low no-load quiescent current 648 nA and a good figure-of-merit score compared to those of previous works, proving that the proposed circuit is an effective solution for use in wearable EEG recording devices.

An approach for designing leakage compensated voltage reference circuit

ABSTRACT In this paper, the design of CMOS-based and recyclic folded cascode (RFC)-based voltage reference circuits is presented. Further inherent leakage compensation technique using diode connected MOSFET is introduced, which results in the compensation of high-temperature leakage current and a reduction in consumed power. Moreover, current mirror-induced mismatch and supply dependency reduces. Furthermore, temperature range and power supply rejection ratio (PSRR) improves. Later, comparison between the two configurations, i.e. with and without leakage compensation, has been presented. The minimum value of the achieved temperature coefficient on applying leakage compensation is 4.2 ppm/ºC for the proposed RFC op-amp-based voltage reference circuit with improved temperature range by 40°C. The obtained value of PSRR is −88.2 dB at 10 Hz, −66.8 dB for 1 KHz and −61.6 dB for 1 MHz frequency, with the line sensitivity of 0.031%/V and the variation of 1.69 mV for an entire operating temperature range. All the simulation results are obtained at 0.7 V supply voltage in 180 nm SCL technology.

Measurement Approach to Evaluation of Ultra-Low-Voltage Amplifier ASICs

Abstract This article presents measurement circuits and a test board developed for the experimental evaluation of prototype chip samples of the Fully Differential Difference Amplifier (FDDA). The Device Under Test (DUT) is an ultra low-voltage, high performance integrated FDDA designed and fabricated in 130nm CMOS technology. The power supply voltage of the FDDA is 400mV. The measurement circuits were implemented on the test board with the fabricated FDDA chip to evaluate its main parameters and properties. In this work, we focus on evaluation of the following parameters: the input offset voltage, the common-mode rejection ratio, and the power supply rejection ratio. The test board was developed and verified. The test board error was measured to be 38.73mV. The offset voltage of the FDDA was −0.66mV. The measured FDDA gain and gain bandwidth were 48dB and 550kHz, respectively. In addition to the measurement board, a graphical user interface was also developed to simplify the control of the device under test during measurements.

High PSR external capacitor‐less LDO with adaptive supply‐ripple cancellation technique

AbstractThis work presents an external capacitor‐less low‐dropout regulator (CL‐LDO) with high power supply rejection (PSR) over a wide frequency and load current ( ) range. The high PSR is implemented with an adaptive supply‐ripple cancellation (ASRC) technique. The proposed ASRC circuit consists of a buffer with diode‐connected structure and an adjusting unit. The novel buffer introduces the supply ripple through the diode‐connected transistor to the gate of the pass transistor, enhancing the PSR in the range of 1 MHz. Additionally, the adjusting unit trims the current of the buffer continuously according to the magnitude of to optimize the PSR adaptively. Designed in a 55 nm CMOS process with an input voltage of 1.4 V, the proposed LDO achieves −69 dB and −55 dB PSR at 100 KHz and 1 MHz for 50 mA of , respectively. Moreover, the maximum current efficiency of the LDO is 99.8% at a full of 50 mA.

A low‐power low‐dropout regulator with improved transient response and power supply rejection

SummaryA high‐precision fast‐settling low‐dropout (LDO) regulator has been presented in this paper. A novel frequency compensation scheme has been proposed to acquire wider bandwidth while sufficient stability is guaranteed for all loading conditions without using external compensation capacitors. Moreover, novel auxiliary circuits have been proposed to improve the slew rate and minimize the settling time. The new LDO has been designed in a standard 0.18‐μm CMOS process. Postlayout simulation results show that the LDO achieves 2.7‐ and 2.48‐MHz unity‐gain frequency for 100 and 0 mA of load current, respectively, while the minimum phase margin is 64°. The results also demonstrate that the worst‐case settling time is almost equal to 1.95 μs. It is shown that by using the new slew rate enhancement technique, the settling time has been reduced from 18 to 1.9 μs. The LDO consumes a quiescent current of 21.5 μA, and the power supply rejection is −46 dB at 10‐kHz offset, which makes the LDO capable of adequately suppressing input supply ripples. The large loop gain of the proposed circuit improves the accuracy of the LDO, and the load and line regulations are 0.1 mV/mA and 0.1 mV/V, respectively.

METHOD OF MEASURING PSRR FOR LINEAR VOLTAGE REGULATORS

The article describes a method for measuring the power supply rejection ratio and its characteristics. A simulation of the measurement in the LTspice program considering a linear voltage regulator as an example, with varying output capacitance is studied.

A Fully Integrated, Domino-Like-Buffered LDO Regulator With High Power-Supply Rejection Across the Full Frequency Spectrum

A Fully Integrated, Domino-Like-Buffered LDO Regulator With High Power-Supply Rejection Across the Full Frequency Spectrum

A High-Precision Bandgap Reference with Chopper Stabilization and V-Curve Compensation Technique.

The MEMS sensor converts the physical signal of nature into an electrical signal. The output signal of the MEMS sensor is so weak and basically in the low-frequency band that the MEMS sensor interface circuit has a rigorous requirement for the noise/offset and temperature coefficient, especially in the bandgap reference block. However, the traditional amplifier has low-frequency noise and offset voltage, which will decrease the precision of the bandgap reference. In order to satisfy the need of the MEMS sensor interface circuit, a high-precision and low-noise bandgap reference is proposed in this paper. A novel operational amplifier with a chopper-stabilization technique is adopted to reduce offset and low-frequency noise. At the same time, the V-curve compensation circuit is used to realize the second-order curvature compensation. The circuit is implemented under the 0.18 μm standard of the CMOS process. The test result shows that the temperature coefficient of the bandgap is 2.31 ppm/°C in the range of -40-140 °C, while the output voltage noise is only 616 nV/sqrt(Hz)@1 Hz and the power-supply rejection ratio is 73 dB@10 kHz. The linear adjustment rate is 0.33 mV/V for supply voltages of 1.2-1.8 V at room temperature, the power consumption is only 107 μW at 1.8 V power supply voltage, and the chip active area is 0.21 × 0.28 mm2.

A Compact MEMS Microphone Digital Readout System Using LDO and PPA-Less VCO-Based Delta-Sigma Modulation Technique

This paper presents a compact Micro-Electro-Mechanical System (MEMS) microphone digital readout system. The system is characterized by a low-dropout regulator (LDO) and a pre-amplifier and programmable-gain amplifier (PPA)-less voltage controlled oscillator (VCO)-based ΔΣ modulation technique, which improve compactness and design scalability. Specifically, to improve signal accuracy and maintain loop stability without a gain-tuning range trade-off, an active low pass filter (ALPF) and a current mode feed-forward path (CMFFP) are incorporated in a VCO-based delta-sigma modulation loop. By means of VCOs and SCG phase variation robustness and current source array feedback (CSAFB), the system achieves a high power supply rejection ratio (PSRR) and gain tuning without the need to design an extra regulator and PPA. The design was fabricated using a 180 nm Bipolar-CMOS-DMOS (BCD) process and measured at a 1.2 V supply voltage. According to the measurement results, the signal-to-noise and distortion ratio (SNDR) achieves 62 dB@1 kHz with 40 dB gain and a 10 kHz bandwidth. Furthermore, PSRR@1 kHz is below −55 dB, and power dissipation is within 57 µW.

Response surface methodology based synchronous multi-performance optimization of CMOS low-dropout regulator

An easy-to-use efficient auto-design approach to achieve a synchronous optimization and solution for multiple performance objectives of a CMOS low-dropout regulator (LDO) circuit is proposed. As a core algorithm, response surface methodology (RSM) is adopted to automatically implement the design parameter modeling and solving of the LDO. The precision response surface models for the temperature coefficient (TC) and power supply rejection ratio (PSRR) are established efficiently based on only 27 sets of Cadence sampling datasets, by which the optimal performance solution with a superior tradeoff on TC and PSRR can be obtained. Along with a complete auto-design flow, the pre/post-layout simulations of the LDO circuit by SMIC 180 nm/3.3 V CMOS technology are performed, it can be observed that the auto-improved LDO has a significant better 35.20 ppm/°C TC feature compared with 48.46 ppm/°C that recorded by the manual design. Synchronously, the PSRR is improved from −59.497 Hz@DC to −92.89 Hz@DC with a great increase ratio by 56 % up.

Biopotential multi-path current feedback instrumentation amplifier with automatic offset cancellation loop for resistive bridge microsensors

<span lang="EN-US">This study introduces a refined current feedback instrumentation amplifier (CFIA) specifically designed for amplifying biopotential signals that originate from resistive-bridge sensors. The proposed architecture uniquely incorporates a multipath chopper-stabilized CFIA which has been developed to minimize the effects of bridge offsets, while maintaining low power usage, high input impedance, and reduced noise characteristics. The engineering blueprint employs a ripple reduction loop (RRL) to mitigate output ripple caused by chopper up-modulation. To speed up offset cancellation and to limit the offset caused by bridge mismatch, an automatic offset cancellation loop (AOCL) circuit is integrated within the analog front end (AFE). Crafted using a conventional 0.18 µm CMOS process, the CFIA in this design provides adjustable gain between 20.35 dB to 55.14 dB, with a power supply rejection ratio (PSRR) and a common mode rejection ratio (CMRR) of 103 dB and 114 dB, respectively. The system demonstrates an input-referred noise (IRN) value of 16 ηV/√Hz at 200 Hz frequency, equivalent to a noise efficiency factor (NEF) of 5.18. Operating from a supply voltage of 1.8V, the AFE shows a power consumption of 291 μW.</span>

A high performance CMOS voltage reference in one simple circuit

This article introduces a novel CMOS threshold voltage reference with low temperature coefficient (TC) and high power supply rejection ratio (PSRR). A novel structure consisting of the Beta-multiplier and an operational amplifier is used to reduce the influence of power supply ripple on output reference voltage VREF and improve PSRR. A 1.2-V MOS transistor and a 3.3-V MOS transistor are employed to achieve temperature compensation and low TC for the output reference voltage VREF, through the difference in threshold voltage. The proposed voltage reference was designed and simulated using a 90 nm CMOS process, occupying a compact active area of 0.003 mm2. Post-simulation results confirm that the voltage reference output is 494 mV, exhibiting a mean TC of 12.58 ppm/∘C across a temperature range from −40∘C to 125∘C. It consumes a mere 461.4 nA when supplied with 1.2 V at 27∘C. Over a supply voltage range of 0.8 – 1.32 V, the line sensitivity (LS) measures 0.57 mV/V. Remarkably, it achieves a high PSRR exceeding −85.6 dB at 100 Hz.

A high PSR and high-precision current-mode bandgap reference with gm boost self-regulated structure

A high power supply rejection and high-precision current-mode bandgap reference system with a reliable start-up gm boost self-regulated structure is presented in this paper. The gm boost technology and high-precision compensation structure are adopted to improve the power supply rejection and precision of the output reference current, respectively. The proposed reference system has been designed in Semiconductor Manufacturing International Corporation (SMIC) 55 nm CMOS process. The simulation results show that with a supply voltage of 3.3 V, the power supply rejection is −101.3dB@DC, −60.23dB@1MHz and −55.6dB@10MHz, the temperature coefficient of the output reference current of proposed circuit is approximately 3.14 ppm/°C in a temperature range from −40 to 125 °C, the quiescent current consumption is 47.8 μA and the silicon area is 0.0992 mm2.

A [formula omitted]104 dB PSRR and 1.86-ppm/[formula omitted] curvature-compensated bandgap voltage reference with improved voltage-self-regulating technology

A high power supply rejection ratio (PSRR) bandgap voltage reference (BGR) with low temperature coefficient (TC) is proposed. The PSRR is enhanced by an improved voltage-self-regulation (VSR) technology which provides a low-impedance branch and negative feedback loop. Furthermore, a curvature compensation structure is proposed to reduce the TC by utilizing the curvature-corrected current (ICU). The proposed BGR supply voltage range is 2.5–3.6 V and its output voltage is 1.2 V. The results of the simulation using a standard 65 nm CMOS process with 3.3 V thick oxide device demonstrate that the line regulation of the proposed BGR is approximately 0.015 mV/V in the supply voltage range of 3–3.6 V. A TC of 1.86 ppm/∘C is obtained in the temperature range of -40∘C to 125∘C, and PSRR of -104 dB@DC are achieved. The active area of the proposed BGR is 0.063 mm2.

Offset Voltage Reduction in Two-Stage Folded-Cascode Operational Amplifier Using High-Precision Source Degeneration

The demand for CMOS precision operational amplifiers for critical applications has continuously increased over time due to higher accuracy and sensitivity requirements. Trimming or chopper architectures are advanced solutions that reduce the offset voltage and improve the circuit’s parameters, but the complexity and the increased chip die size are serious downsides. An efficient solution is a source degeneration configuration to control the transistor’s current-mirror transconductance, which impacts the offset voltage, with cost savings and a die area reduction also obtained. This paper focuses on designing and implementing such an approach in a two-stage folded-cascode operational amplifier. State-of-the-art thin-film resistors that use silicon–chromium as the metallic alloy were implemented to reduce mismatch variations between these passive components. Distinct methods that control the offset voltage parameter are also discussed and established. A comparison between the offset voltage standard deviation obtained using different types of resistors and that achieved with the innovative high-precision resistors was also carried out. The source degeneration’s impact on the common-mode rejection ratio, power supply rejection ratio, bandwidth and phase margin was also analyzed, and a comparison between the proposed design and the classical one was performed. The process variation’s influence on the circuit functionality was studied. A pre-layout ±1.273 mV maximum offset voltage at T = 27 °C was achieved using vector/array notations for the amplifier with the best overall performance. Post-layout simulations that included parasitic effects were performed, with a ±1.254 mV maximum offset voltage reached at room temperature.

Design of a High PSRR Low-pressure Bandgap Reference Source with Curvature Compensation

Based on the NUVOTON 0.35 μm BCD process, a low voltage bandgap reference with an input voltage of 5 V and output voltage of 0.6 V is designed in this paper. The traditional low-voltage bandgap reference output voltage has a large temperature coefficient and poor ability to suppress power supply fluctuations. In this paper, a circuit with high order compensation is proposed to reduce the temperature coefficient of the circuit, and a pre-regulated circuit is used to increase the power supply rejection ratio. The simulation results are at -30 °C∼130 °C. The output voltage of reference voltage is 947.5 μV, the temperature coefficient is 9.58 ppm/°C, and the power suppression ratio is -104.62 dB, which meets the design requirements of the power management chip.

A Capacitorless LDO Regulator with Fast Feedback Loop and Damping-Factor-Control Frequency Compensation

A fast feedback loop (FFL) based on comparators is proposed in this paper. The FFL improves the transient response characteristics of the output-capacitorless low-dropout (OCL-LDO) regulator. When the load current switches between 1 mA and 100 mA with 1 μs edge time, the overshoot and undershoot are 33 mV and 37 mV, respectively, and recovery time is 1.2 μs and 1.6 μs, respectively. A damping-factor-control (DFC) frequency compensation circuit is used to ensure the stability of the OCL-LDO, and the simulation results show that the phase margin exceeds 50 degree in the entire load variation range. This design is based on 180 nm process, and the area of the chip is 0.068 mm2 (without pads). A band-gap reference circuit is also designed in this work; its output voltage is 1.2 V and its temperature coefficient is 7.96 ppm/∘C. The input voltage range of the proposed OCL-LDO is 2.5 V to 5 V with a linear regulation rate of 0.128 mV/V and a load regulation rate of 0.0017 mV/mA. In addition, the load range of the proposed OCL-LDO is 0 mA to 100 mA, and the minimum required external capacitance is 0 F. The power supply rejection ratio (PSRR) is −46 dB @ 1 kHz.

A high-accuracy voltage reference with high-order curvature compensation and base-current-canceling techniques

This paper presents a low dropout bandgap voltage reference circuit that combines high output voltage accuracy and low temperature-coefficient in a wide temperature range. The low temperature-coefficient is achieved by an advanced high-order curvature compensation technique, which is implemented by a novel exponential piecewise compensation term in a high-temperature range. A supply noise self-regulation technique is proposed to realize an excellent power supply rejection ratio (PSRR) without using any amplifiers in this paper. The proposed high-accuracy voltage reference is designed in a 2[Formula: see text][Formula: see text]m bipolar process. The circuit generates a reference voltage of 3.3[Formula: see text]V and can operate under a minimum supply voltage of 3.8[Formula: see text]V, while consuming 44.8[Formula: see text][Formula: see text]A. The output voltage accuracy is ± 0.15%. The PSRR at 10[Formula: see text]Hz and 1[Formula: see text]MHz is [Formula: see text][Formula: see text]dB and [Formula: see text][Formula: see text]dB, respectively. The line regulation is 2.45[Formula: see text]ppm/V in a supply voltage range from 3.8[Formula: see text]V to 20[Formula: see text]V. The average temperature coefficient is 11.9[Formula: see text]ppm/∘C in a temperature range from [Formula: see text]C to +125∘C.

A 54 µW CMOS Auto-Trimming Bandgap References (ATBGR) Achieving 90 dB PSRR for Artificial Intelligence of Things (AIoT) Chips.

An Auto-Trimming CMOS Bandgap References Circuit (ATBGR) with PSRR enhancement circuit for Artificial Intelligence of Things (AIoT) chips is presented in this paper. The ATBGR is designed with a first-order temperature compensation technique providing a stable reference voltage of 1.25 V in the ranges of input voltages from 1.65 V to 4.5 V. An auto-trimming circuit is integrated into a PTAT resistor of BGR to minimize the influences of the process variations. The four parallel resistor pairs with PMOS switches are connected in series with the PTAT resistor. The reference voltage, VREF, is compared to an external constant value, 1.25 V, through an operational amplifier, and the output of the de-multiplexer is used to configure the PMOS switches. High power supply rejection is achieved through a PSRR enhancement circuit constituting a cascaded PMOS common gate pair. The ATBGR circuit is fabricated in 180 nm CMOS technology, consuming an area of 0.03277 mm2. The auto-trimming method yields an average temperature coefficient of 9.99 ppm/°C with temperature ranges from -40 °C to 125 °C, and a power supply rejection ratio of -90 dB at 100 MHz is obtained. The line regulation of the proposed circuit is 0.434%/V with power consumption of 54.12 µW at room temperature.