Design of a LDO with High PSRR

Abstract

One of the common ways to increase the PSRR(power supply rejection ratio) of LDO (low dropout linear regulator) is increasing the gain of error amplifier, but the stability of LDO system will also be reduced. A new high gain error amplifier is designed to push the poles inside the amplifier away from the origin, which ensures the stability of LDO system and improves the PSRR of low frequency band. At the TT process corner, the range of adjustable output voltage of LDO is 1.361~1.860 V under the simulation condition of 27 °C. When power supply ranges from 2.3 V to 3.3 V, the linear regulation rate is 238.3 µV/V; When the load changes from 0 to 20 mA, the load regulation rate is 9.6 µV/mA; At load current of 20 µA, the power supply rejection ratio of LDO is -97 dB@dc, and the phase margin of the whole circuit is greater than 66 degrees. The chip is verified in a 0.18 µm CMOS process. Setting the power supply voltage in the range of 2.3 to 3.3 V, the output voltage is stable at 1.8 V, and the error is only 1.9 mV, which is less than 0.2%.