A Low Power Low Inrush Current LDO with Different Techniques for PSR and Stability Improvement

Abstract

One of the most popular power management regulators is the low drop-out voltage regulator (LDO). LDOs have different specifications such as the power supply rejection (PSR) over different frequencies, stability over different load ranges, inrush current spike flows through the input supply, and power consumption. In this work, we present a low power low inrush current LDO design with different techniques for PSR and stability improvement across different frequencies. The LDO presented in this work is a low-power and small area LDO but achieves a high PSR over a wide range of frequencies. The LDO is designed in 65 nm CMOS technology and achieves a PSR better than 80 dB up to 30 MHz for an output load current of 25 mA using an output load capacitor of 4 µF. The design can be used in capless/capped LDOs with wide load current ranges as high as 200 mA and load capacitor range from 1 nF to 12 µF with inrush current improvement by more than 2×. The presented LDO consumes a zero-load quiescent current of 10 µA and its area of 180 µm × 180 µm.