Power Supply Rejection Research Articles

A Direct Battery Hookup Filterless Pulsewidth Modulation Class D Amplifier With >100 dB PSRR for 100 Hz to 1 kHz, 0.005% THD+N and 16 μV Noise

Due to ever-increasing demand for high-level integration, low power dissipation and high fidelity, Class D amplifier ICs (CDA ICs) need to feature very high power supply rejection ratio (PSRR), very low total harmonic distortion plus noise (THD + N), low output noise, high power-efficiency, low electromagnetic interference (EMI), and fixed switching frequency. We propose a fully integrated filterless CDA IC embodying a novel loop-filter that simultaneously features an ultrahigh loop gain of >200 dB and high carrier attenuation of −10 dB. Due to the ultrahigh loop gain and high carrier attenuation, the linearity and PSRR of the CDA IC is significantly improved. The proposed CDA IC further embodies a novel deadtime circuit that can eliminate the false switching in the Class D output stage, hence reducing the EMI and further improving the linearity of the CDA IC. The proposed CDA IC simultaneously features an ultrahigh PSRR (>100 dB from 100 Hz to 1 kHz), very low THD + N (0.005%), very low output noise (16 μV), and low EMI (10 dB below the EN55022 Class B standard)—yet with fixed switching frequency (400 kHz). When benchmarked against state-of-the-art designs, our CDA IC features the highest PSRR, allowing hookup directly to the battery and features the lowest output noise.

Exploring the Advantages of Single-Ended-Input CMOS Self-Biased Amplifiers

This brief presents the analysis of self-biased topologies to implement single-ended-input CMOS amplifiers. We depart from basic amplifying stages to construct the self-biased circuits. We propose an amplifier based on the common-source and cascode configurations with active load, in which all three transistors are self-biased. This translates into important advantages for the amplifier: less power consumption since biasing circuits are no needed, and a robust design because all transistors are guaranteed to be in the saturation region even with process, temperature, or supply variations. The only drawback of this topology is the low power-supply rejection. A prototype was designed in a 130-nm CMOS technology to have a gain of 40 dB in the frequency band between 100 kHz and 5 MHz. The measurements of the circuit demonstrated that the amplifier fulfilled the specifications at the nominal voltage (1.2 V) while consuming 13 $\mu \text{A}$ . Furthermore, the circuit functions as amplifier for supply voltages as low as 400 mV and such high as 1.5 V, probing the flexibility of self-biased circuits. That flexibility can be explored in the future to design adaptive systems and to facilitate analog design automation.

The high recycling folded cascode (HRFC): A general enhancement of the recycling folded cascode operational amplifier

In this paper, an enhanced CMOS recycling folded cascode (RFC) operational amplifier (Op-Amp) is presented. It is based on the high recycling folded cascode (HRFC) in amplifying the transconductance at the output by shorting two nodes in the RFC structure. Compared to the conventional RFC, our circuit is capable to enhance DC gain and unity gain bandwidth (UGBW) in the same power consumption. Moreover, the improvements of the proposed circuit are in better input-referred noise, fast-settling time, input-offset voltage, total harmonic distortion (THD), common mode rejection ratio (CMRR) and power supply rejection ratio (PSRR). Simulation results in 180 nm CMOS standard technology confirm the theoretical results and indicate that our circuit has a good figure of merit (FoM). Compared to the RFC, the proposed HRFC has 1.8 times the UGBW (247 versus 137 MHz) and also has 6 times gain boosting (73 versus 57 dB) in the same power supply (1.8 V), power consumption and driving capacitor load of 5 pF.

A compact power-efficient 0.5 V fully differential difference amplifier

This brief presents a novel compact CMOS Fully Differential Difference Amplifier (FDDA) structure suitable for extremely low-voltage low-power applications. Unlike the conventional FB-DDAs that employ two differential pairs, the proposed structure employs one differential pair of multiple-input bulk-driven MOS transistor (MI-BD MOST) that results in reduced count of current branches and, consequently, of power consumption. The proposed FDDA has the simplest CMOS structure presented in the literature so far. Furthermore, while the voltage supply is 0.5 V and the power consumption is 246.6 nW the circuit enjoys rail-to-rail input common mode range (ICMR), high common mode rejection ratio (CMRR) of 100.3 dB @ DC, power supply rejection ratio (PSRR) of 127.8 dB@ DC, voltage gain of 61.4 dB and gain bandwidth product of 6.98 kHz for 30 pF capacitive load. The total harmonic distortion (THD) is less than 0.08% for 500 mV/1 kHz input sine wave signal. The circuit was designed and simulated in Cadence/Spectre environment using 0.18 µm CMOS process from TSMC.

A Low Power Analog Front-End of BJT-based Temperature Sensor for Implanted RFID

In this paper, a low-power analog front-end (AFE) of BJT-based temperature sensor for implanted Radio Frequency Identification (RFID) is designed. Firstly, the architecture of BJT-based temperature sensor is described. Then a low-power bias circuit in the AFE is proposed to reduce the power consumption, and the bipolar core is optimized to improve the inaccuracy of temperature sensor. At last, the simulation is performed and the chip is fabricated in SMIC 0.18μm technology. The current is 2.6μA with a supply voltage of 1.8V and the current is 1μA when the circuit is disabled. The inaccuracy is 0.6°C from 25°C to 45°C. The power supply rejection ratio (PSRR) is 50dB at DC and 37dB at 1MHz respectively.

Optimization of CMOS Miller OTA using Differential Evolutionary Algorithm

The circuit parameters of CMOS based analog and mixed-signal circuits conventionally are achieved by skilled engineers. Due to the progress of Moore’s assumption and the growing complication of physical MOSFET models, the attention towards automation of CMOS based analog circuit design is increased. The issue of the automatic design of analog circuit has been tracked in the academy and industry since more than last two decades. In this paper, application of differential evolution (DE) algorithm is presented for the optimization of CMOS Miller Operational Transconductance Amplifier (OTA). DE algorithm has been developed using C language to optimize the CMOS Miller OTA. The error function of optimization for this circuit depends on desired specifications like voltage gain, phase margin (PM), unit gain bandwidth (UGB), power consumption, common mode rejection ratio (CMRR), slew rate (SR), power supply rejection ratio (PSRR), and a total MOS transistor area. Ngspice circuit simulator has been used as an error function creator and evaluator. BSIM3v3 MOSFET models with 0.18 µm and 0.35 µm CMOS technology have been used to simulate this circuit. The simulation results of this work are presented and compared with previous works reported in the literature

A 99.96% efficiency capacitor-free low-dropout regulator with cross-couple class-AB push–pull input stage for wireless internet of things chip

A high efficiency capacitor-free low-dropout regulator (LDO) with the cross-couple class-AB push–pull input stage is presented for wireless internet of things and wireless senor network chip. Utilizing the proposed input stage, both load/line regulation and power supply rejection ratio (PSRR) are improved. Meanwhile, the transient response including the undershoot voltage, the overshoot voltage and the recovery time is optimized with the sub-threshold slew-rate enhancement circuit and the multiple loop compensation strategy. Simulation results show that the LDO only consumes a quiescent current of 41.8 μA, resulting in the energy efficiency of 99.96% at a 100-mA maximum load current (IL) from 1.2 V supply voltage using 0.18-μm CMOS process. When IL is switching from 0 A to 100 mA in 0.3 μs, the undershoot voltage and the overshoot voltage are about 131.62 mV and 126.31 mV while the corresponding recovery time are 0.77 μs and 0.55 μs with CL = 100 pF, respectively. Furthermore, PSRR at 1-kHz is boosted to − 58.8 dB at full load. Besides, an excellent line and load regulation of 0.24 mV/V and 1.76 μV/mA are obtained, respectively.

A 42-dB$\Omega~25$ -Gb/s CMOS Transimpedance Amplifier With Multiple-Peaking Scheme for Optical Communications

This brief presents a low-power, broadband, inverter-based transimpedance amplifier (TIA) design employing the input series peaking and shunt–shunt inductive feedback in a 65-nm CMOS process. The design optimization of the TIA core amplifier is described in detail. The proposed multiple-peaking scheme incorporates an input bond-wire and two on-chip inductors to mitigate the photodetector capacitive loading, achieving an overall bandwidth enhancement ratio of 2.8. A transimpedance gain of 42 dB $\Omega $ is measured up to 24 GHz without the off-chip photodetector capacitance. A low-dropout regulator (LDO) with full-spectrum power supply rejection is integrated to suppress supply noise and parasitic effect due to the power supply bond-wires. Optical measurements at 25 Gb/s show that the data eye RMS and peak-to-peak jitters are improved by 15% and 24%, respectively, when the LDO is enabled. The measured TIA sensitivity is −7.3 dBm at 25 Gb/s with a BER $ for a $2^{{15}}{-}1$ PRBS optical input. The 1-V TIA with on-chip LDO consumes 3 mW from a 1.2-V external power supply.

Analog-Assisted Digital Capacitorless Low-Dropout Regulator Supporting Wide Load Range

Capacitorless (CL) low-dropout regulators (LDO) have gained significant research interest for point-of-load voltage regulation without off-chip capacitors. While analog CL-LDOs can deliver superior power supply rejection (PSR), digital CL-LDOs are more scalable and efficient. To achieve the advantages of both types, this paper presents a digital CL-LDO with an analog PSR enhancer, delivering strong PSR without compromising scalability and efficiency. Load regulation is performed by an asynchronous digital feedback controller for fast transient response and scalable load drivability. PSR is achieved by a load-insensitive wide-bandwidth analog controller. A prototype chip of the analog-assisted digital CL-LDO is fabricated in a 130-nm CMOS process with an active area of 0.0645 mm2 , supporting load current up to 50 mA at nominal 1-V input and 0.8-V output. The measured PSR is better than –20 dB for frequencies up to 10 MHz, and the measured current efficiency peaks at 99.3%, with average current efficiency of 96.7% across 50× load range. The measured transient response to a full load step, with two values of load capacitance (100 pF and 10 nF), demonstrates the LDO's stable operation over a wide range of load resistance and capacitance.

A Design With High Order Compensation and low Temperature Drift Bandgap Reference Voltage Source

Based on the analysis of the conventional bandgap reference circuitry and the current IC of reference voltage source in the design of low voltage low power consumption and high power supply rejection ratio, a bandgap voltage reference with startup circuit and current compensation circuit is presented. It has a low temperature coefficient(<20ppm/℃)，a temperature coefficient of 9.3ppm/℃ in the temperature range from-50℃ to 125℃, and a PSRR of-64dB at low frequency,which meets the requirements of bandgap reference for low voltage, low power and high PSRR.

A Sub-1 V Temperature-Insensitive-PSR Bandgap Reference with Complementary Loop Locking

This paper presents a novel low-voltage bandgap reference with improved power supply rejection (PSR). The proposed circuit adopts a complementary loop locking approach for stabilizing the drain-source voltages of the current mirrors, which gives rise to a boost of the PSR performance by more than 30[Formula: see text]dB over [Formula: see text]–110∘C and at 1-V supply. An analysis shows that the PSR of the proposed bandgap reference is typically characterized with its insensitivity to temperature variations. The circuit is designed with a commercial 0.18-[Formula: see text]m CMOS process. The experiment results of Monte Carlo simulation demonstrate that the average PSR with 1-V supply is [Formula: see text][Formula: see text]dB at DC and is [Formula: see text][Formula: see text]dB at 1[Formula: see text]kHz (attained under a room temperature condition of 27∘C). And the temperature coefficient of the DC-based PSR is about 0.83%/∘C at 1-V supply, significantly decreased by three–six folds compared to other conventional designs. The quiescent current consumed is only about 13.5[Formula: see text][Formula: see text]A.

A 12-bit 350 MS/s Single-Channel Pipeline ADC with 75 dB SFDR in 0.18 μm BiCMOS

A 12-bit 350[Formula: see text]MS/s ADC with 75[Formula: see text]dB SFDR fabricated in 0.18[Formula: see text][Formula: see text]m SiGe BiCMOS process is presented. To improve the power efficiency, the ADC employs a novel residue amplifier (RA) by exploiting the hetero-junction bipolar transistor (HBT). We also propose a fast comparator to save time for the residue settling of pipeline stages. A fully integrated reference buffer with “negative bootstrap power” (NBP) is proposed to improve both high power supply rejection ratio (PSRR) and ground supply rejection ratio (GSRR). A bandgap reference (BGR) with ultra-low leakage current start-up loop is also presented. The measured results show that with Nyquist input, the SFDR achieves 75[Formula: see text]dB and 63[Formula: see text]dB SNDR up to 350[Formula: see text]MS/s and consumes 180[Formula: see text]mW (only ADC core) with 580[Formula: see text]fj/cov Waldon FOM.

16.8/15.2 ppm/°C 81 nW High PSRR Dual-Output Voltage Reference for Portable Biomedical Application

A dual-output voltage reference circuit with two reference voltages of 281 mV (Vref1) and 320.5 mV (Vref2) is presented in this paper. With a novel and precise circuit structure, the proposed circuit, operating in the subthreshold region, integrates two different output voltages into a circuit to form a dual-output voltage reference, and cascode current mirrors are used to enhance the power supply rejection ratio (PSRR). The proposed circuit was designed in a standard 0.18-µm CMOS process and has a series of attractive features: low-temperature coefficient (TC), high-PSRR, low-Line sensitivity (LS), small-chip area and low-power consumption. Monte Carlo simulations for 2000 samples showed that the output voltages 281 mV and 320.5 mV had a variation coefficient of 1.73% and 1.44%, respectively. The minimum power consumption was 84.1 nW at 0.9 V supply, proving that the circuit is suitable for portable biomedical application. The active area of the proposed voltage reference was only 0.0086 mm2.

A CMOS Self-Bias CTAT Current Generator with Improved Supply Sensitivity

The role of complimentary to absolute temperature (CTAT) circuit in current mode bandgap has been described. Loop-gain problems with the existing self-bias MOS-based CTAT generator were discussed. A simple modification to the existing circuit was proposed to enhance the loop-gain by [Formula: see text]20[Formula: see text]dB without adding additional circuitry leading to zero additional power consumption. Power Supply Rejection and sensitivity to [Formula: see text] will be improved due to the higher loop-gain. A prototype has been developed to demonstrate the proposal robustness across PVT corners. Simulation results show 20.5[Formula: see text]dB PSRR improvement and 7.5% improvement in sensitivity to [Formula: see text]. The proposed solution consumes 180[Formula: see text]nW power from 1[Formula: see text]V power supply voltage and occupies 3300[Formula: see text][Formula: see text]m2 silicon area.

An enhanced fast slew rate recycling folded cascode Op-Amp with general improvement in 180 nm CMOS process

This paper presents a new technique to improve CMOS recycling folded cascode (RFC) operational amplifier (Op-Amp). Our modification is based on shorting two nodes in the conventional RFC circuit. It causes that the seen resistance from the created new node be half of the conventional RFC counterpart and makes it to double the slew rate. Compared to it, our circuit is also capable to enhance DC gain and unity gain bandwidth (UGBW) with increasing output resistance of differential pair. Moreover, our proposed improvements are in better fast-settling time, input referred noise, input offset voltage, total harmonic distortion (THD), common mode rejection ratio (CMRR) and power supply rejection ratio (PSRR) in the same power consumption. Simulation results in 180 nm CMOS process indicates that the proposed amplifier has 1.5 times the unity gain bandwidth (185 MHz versus 125 MHz) and also has 7 times gain boosting (75 dB versus 58 dB) with better figure of merit (FOM) in the same power consumption, driving capacitor load of 10 pF @1.2 V power supply. The results also demonstrate that the temperature sensitivity, power supply variations and process corners have a negligible effect on the proposed amplifier stability.

A High-Precision Bandgap Voltage Reference with Automatic Curvature-Compensation Technique

A high-precision bandgap voltage reference (BGR) with a novel curvature-compensation scheme is proposed in this paper. The temperature coefficient (TC) can be automatically optimized with a built-in adaptive curvature-compensation technique, which is realized in a digitization control way. An exponential curvature-compensation method is first adopted to reduce the TC in a certain degree, especially in low temperature range. Then, the temperature drift of BGR in higher temperature range can be further minimized by dynamic zero-temperature-coefficient point tracking (ZTCPT) with temperature changes. With the help of proposed adaptive signal processing, the output voltage of BGR can approximately maintain zero TC in a wider temperature range. Verification results of the BGR proposed in this paper, which is implemented in 0.35-[Formula: see text]m BiCMOS process, illustrate that the TC of 1.4[Formula: see text]ppm/∘C is realized under the power supply voltage of 3[Formula: see text]V and the power supply rejection of the proposed circuit is [Formula: see text][Formula: see text]dB without any filter capacitor.

A High Power Supply Rejection and Fast Settling Time Capacitor-Less LDO

This paper presents an internally compensated capacitor-less low dropout regulator (CL-LDO) with bulk-driven feed-forward supply noise cancellation and adaptive compensation for fast settling time (TS ). A feed-forward path from the CL-LDO's supply input to the output is implemented to increase power supply rejection (PSR) from mid-range frequencies to up to 5 MHz. The CL-LDO achieves a -90 dB low frequency and -64 dB PSR at 1 MHz for 50 mA of load current (IL). A transconductance amplifier with adaptive Miller compensation based on IL sense is used to increase the unity-gain frequency by 40× at heavy loads. The CL-LDO achieves a 0.3 mV/V line regulation, 10 μV/mA load regulation, 300 ns of TS, and 0.16 ps figure of merit, which is 7.5× better than current state-of-the-art CL-LDOs. The CL-LDO was fabricated in CMOS 130 nm technology, consumes IQ of 42 μA, has a dropout voltage (VDO) of 200 mV for IL of 50 mA, and occupies an active area of 0.0046 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> .

Systematic Design of Bandgap Voltage Reference Using Precomputed Lookup Tables

Bandgap voltage references are indispensable in any analog/mixed-signal system. In this paper, we introduce a systematic gm/ID-based procedure to design a CMOS bandgap reference. The proposed iterative methodology relies on one-time-generated precomputed lookup tables (LUTs); thus, it does not require invoking a simulator in the loop. Despite the inherent finite accuracy of the LUT-based design approach, we demonstrate that a precision bandgap circuit can be designed with less than 1-ppm error. We verified the proposed procedure against the Spectre simulations and probed the design space using a symbolic circuit solver. Moreover, we demonstrated how variations and mismatch can be taken into account in the context of the proposed methodology. The results demonstrate that the proposed procedure can provide very accurate results in a short execution time, enabling the designer to explore the design space of key performance metrics, such as power-supply rejection (PSR) and noise.

A 28 ppm/°C, 2.54 ppm/V, −77 dB@100 Hz pico-ampere voltage reference for high-end IoT systems

This paper presents a pico-ampere voltage reference for IoT systems with high performance in line regulation and power supply rejection ratio (PSRR). Based on the leakage current characteristics of MOSFETs, the reference voltage is obtained by taking advantage of the threshold voltage differences between two types of MOSFETs with different gate oxide thicknesses. By employing a self-regulation technique, the impacts of drain-induced barrier lowering (DIBL), gate-induced drain leakage (GIDL) and gate-drain capacitance feedthrough effects can be mitigated, resulting in high performance in line regulation and PSRR. Based on a 0.18 μm standard CMOS process, post-layout simulation results show the temperature coefficient is 28.0 ppm/°C over the temperature range of 0–120 °C with a 0.6 V supply voltage. The line regulation is 2.54 ppm/V, which is at least two orders of magnitude lower than existing designs in the literature. The PSRR is −77 dB@100 Hz that is improved by at least 10 dB over existing designs in the literature.

A High-Precision Resistor-Less CMOS Compensated Bandgap Reference Based on Successive Voltage-Step Compensation

A curvature-compensated resistor-less bandgap reference (BGR), which is fabricated in 0.5- $\mu \text{m}$ CMOS process, is proposed in this paper. The BGR utilizes successive voltage-step compensation to produce a temperature-insensitive voltage reference (VR), including one $\Delta V_{\text {GS}}$ step for first-order compensation and another one for higher order curvature correction. Moreover, a supply noise bypassing technique is adopted to achieve good power supply rejection performance up to high frequency. Experimental results demonstrate that this BGR is able to produce a VR of 1.196 V with a temperature coefficient of 3.98 ppm/°C at 3.6-V supply voltage. A power-supply noise attenuation of −84 dB@100 Hz and −37 dB@100 kHz are easily achieved, and the line regulation is better than 0.19 mV/V when supply voltage varies from 2.1 to 5 V. The proposed reference occupies an active area of $356 \,\,\mu \text {m} \times 150 \,\,\mu \text{m}$ and consumes a quiescent current of $38~\mu \text{A}$ .