Power Supply Rejection Research Articles

Optimized Power Supply Rejection Ratio Modeling Technique for Simulation of Automotive Low-Dropout Linear Voltage Regulators

In the automotive domain, the vast majority of testing is performed through simulations, which can validate a system design before the actual implementation and can emphasize eventual faults in the design process. Hence, the simulation is of utmost importance. Behavioral models are necessary for the creation of each electronic device desired in the system, and some of the components have very complex behavior: low-dropout linear voltage regulators (LDOs), gate drivers, and switching regulators. In the automotive industry, LDOs are essential components because they power all the other subsystems and very accurate behavior is needed to make sure that the system behaves as in reality. LDO models are already commercially available and most of their intrinsic characteristics are modeled (dropout voltage, line regulation, load regulation, etc.). However, one characteristic that is extremely useful, yet the hardest to model, is the power supply rejection ratio (PSRR). This paper proposes a new PSRR modeling technique for automotive low-dropout voltage regulators. The new PSRR characteristic was modeled for an automotive LDO product in a Texas Instruments portfolio, which has a commercially available model, and was simulated using the PSpice Allegro simulator and the OrCAD Capture CIS environment.

A Sub-1-V CMOS Voltage Reference with High PSRR and High Accuracy

This paper presents a novel sub-1-V CMOS voltage reference with high power supply rejection ratio (PSRR), low line sensitivity, and low supply voltage. CMOS voltage references available in the literature use a self-biased cascode branch consisting of two MOS transistors operating in the subthreshold region to generate the proportional-to-absolute-temperature (PTAT) voltage only, whereas extra circuitry is required to generate the complementary-to-absolute-temperature (CTAT) voltage for temperature compensation. But in the proposed sub-1-V CMOS voltage reference, both the PTAT and CTAT voltages are generated using a single self-biased cascode branch. Two operational amplifiers in negative feedback topology are used to convert the PTAT and CTAT voltages into PTAT and CTAT currents, respectively, which help to enhance the stability and PSRR of the proposed voltage reference. The proposed voltage reference has been designed and simulated in 180-nm standard CMOS technology using Cadence Virtuoso Analog Design Environment. The proposed voltage reference achieves an output reference voltage of 424.85[Formula: see text]mV with a temperature coefficient of 29.5[Formula: see text]ppm/∘C for the temperatures ranging from [Formula: see text]C to 125∘C at a supply voltage of 0.8[Formula: see text]V. A line sensitivity of 0.0035%/V is achieved for the supply voltage varying from 0.8[Formula: see text]V to 5[Formula: see text]V at nominal temperature (27∘C). A PSRR of [Formula: see text]91.69[Formula: see text]dB is observed for the frequencies ranging from 1[Formula: see text]Hz to 10[Formula: see text]kHz at nominal conditions without using any capacitive filter. Also, the output noises of the proposed design at nominal conditions for the frequencies of 1[Formula: see text]Hz and 10[Formula: see text]kHz are obtained as 2.37[Formula: see text][Formula: see text]V/[Formula: see text]Hz and 45.26[Formula: see text]nV/[Formula: see text]Hz, respectively.

A High-Loop-Gain Low-Dropout Regulator with Adaptive Positive Feedback Compensation Handling 1-A Load Current

Low-dropout regulators, which have the capabilities of handling large output current and obtaining a superior transient response, are receiving increasing attention. This paper presents a high-output-current low-dropout regulator with high loop gain. An adaptive positive feedback compensation method is presented. It guarantees stability under full load conditions and achieves high loop gain. Without relying on an external zero, a ceramic capacitor with low equivalent series resistance can be employed, resulting in the minimized output voltage variation during the load transient response. In addition, the load regulation and line regulation are both small. An impedance adapting stage is inserted between the error amplifier and power transistor. It is suitable for low-supply voltage applications and drives the power transistor quickly. The simulation results indicate that the proposed LDO can supply a 1000 mA load current with a 200 mV dropout voltage. The load regulation and line regulations are 0.089 μV/mA and 0.562 m V/V, respectively. The power supply rejection is above 75 dB at 1 kHz under the full range of the output current.

A novel instrumentation amplifier with high tunable gain and CMRR forbiomedical applications

A new design of current mode instrumentation amplifier (CMIA) with tunable gain and low voltage operation capability is proposed in this paper, which is suitable for biomedical signals processing, especially in electrocardiogram (ECG). It consists of a new design of current differencing transconductance amplifier (CDTA) and dual z copy CDTA (DZC-CDTA). The gain of the proposed CMIA is controlled by a MOS-based tunable resistor. The main advantage of the proposed CMIA is its high gain that can be tuned over a significant range with the help of two resistances. The performance of the proposed instrumentation amplifier is evaluated through simulation results on Cadence Virtuoso using SCL 180 nm CMOS technology. From simulation results gain, common mode rejection ratio (CMRR), power supply rejection ratio (PSRR), %THD and -3 dB bandwidth of proposed instrumentation amplifier are obtained as 55.09?81.12 dB, 90.42-116.5 dB, 97.3 dB (+PSRR), 114.2 dB (- PSRR), 1.5% and 9.5-165 kHz, respectively. The performance of the proposed design is also examined against PVT variations. The performance of proposed CMIA is compared with other existing designs available in the literature, which clearly shows the competency of the design. The post layout simulation results confirm the on-chip implementation feasibility.

Fully Electrical Post-Fabrication Trimming of Resistive Sensors.

A compact and efficient IC architecture is presented as an alternative to laser-trimmed precision thin-film resistors or look-up tables. The objective is to keep the device, such as a four-terminal Wheatstone bridge, but to compensate for post-manufacturing offset and to avoid the so-induced degradation of performances in terms of full-scale, non-linearity, power supply noise rejection and scale factor. Expected advantages are a reduced cost due to the electrical-only implementation and a possible on-field calibration of high-end sensors. Application of the proposed solution is illustrated on an example to demonstrate improvement factors on offset and sensitivity accuracy of 32 and 10, respectively. Additionally, the power supply rejection ratio is improved by 30 dB. The experimental results finally demonstrate both efficiency and versatility of the proposed solution thanks to a first silicon prototype, fabricated in a 0.35 μm Technology from AMS, connected to an off-the-shelf pressure sensor.

Evaluation and Perspective of Analog Low-Dropout Voltage Regulators: A Review

Low-dropout regulators (LDOs) are widely adopted in power management integrated circuits (PMICs) and serve as a bridge between the switching regulators and individual on-chip modules to provide a smooth, regulated output voltage. Compared to digital LDOs (DLDOs), analog LDOs (ALDOs) lead in the advantage of low output ripple and large power supply rejection (PSR). However, the preference of achieving high performance in terms of load transient, high PSR, good load and line regulation, while maintaining a low quiescent current and low dropout voltage for high efficiency, remains the key challenge in ALDO design. For operation with a low quiescent current, the bandwidth is reduced due to low transconductance, resulting in the limited gate driving capabilities in terms of charging and discharging the large gate capacitance of the pass or output transistor. In addition, the preference for system-on-chip design in the absence of large off-chip capacitors arises stability issues. In this paper, recent reported state-of-the-art architectures for ALDOs are revisited and reviewed. The performance of these ALDOs is compared and their applications are investigated.

Comparative Performance Study of Difference Differential Amplifier Using 7 nm and 14 nm FinFET Technologies and Carbon Nanotube FET

Difference differential amplifiers (DDA), which were built on FinFET and carbon nanotube FET (CNTFET), are frequently used for signal processing owing to their advantages of low‐power dissipation and reduced device dimension. In this work, high‐performance DDA was established using CNTFET model parameters as well as FinFET 7 nm and 14 nm technology. The DDA circuit used in this scenario was identically the same to the one used previously. With the use of Verilog AMS code‐based Stanford model parameters applied CNTFET and 7 nm and 14 nm FinFETs, schematic capture and simulations of the DDA were carried out in the Symica environment. The mostly used measurements for assessing the performance of operational amplifiers were also adopted for DDA. The CNTFET‐based difference differential amplifiers have slew rates of 10.8 V/femtosecond and 11.2 mV/femtosecond, respectively, with settling times of 0.65 femtosecond and 0.43 femtosecond, respectively. The power supply rejection ratio (PSRR) is 2.53 dB with a dynamic range of 198 mV and 6 mV for CNTFET DDA operating at 0.6 V DC. The incentives of CNTFET appropriateness for DDA designed in this study for any analogue front end were further demonstrated by using CNTFET for DDA with the achievement of open loop differential gain of 116.03 dB with BW of 4 GHz and phase margin of 270 and common mode gain of ‐28.65 dB with BW of 55.14 MHz and phase margin of 270.

A Fully MOSFET Voltage Reference with Low Power Consumption and High Power Supply Rejection Ratio for IoT Microsystems

In this work, a fully MOSFET voltage reference (FMVR) circuit with a current consumption of 7.6 nA and a supply voltage of 1 V is proposed. To generate the complementary to absolute temperature (CTAT) voltage, the voltage of a PN junction generated by a PMOS transistor - which is part of the bias circuit - is used. Generation of proportional to absolute temperature (PTAT) voltage is carried-out by utilizing three stages of self-cascode transistors biased in the sub-threshold region. A fraction of the CTAT voltage is added to the PTAT voltage without using an additional circuit to enable acquiring an output reference voltage of about 0.648 V with minimal temperature dependence. The proposed voltage reference is simulated in 0.18 μm of CMOS process and its area occupation is 0.0023 mm2. The obtained post-layout simulation results demonstrate that the proposed FMVR has a temperature coefficient equivalent to 12.9 ppm/°C under the temperature variation from -25 °C to 120 °C. Moreover, the line regulation under supply voltage variation from 0.9 V to 2 V is found to be equal to 0.02 %/V, and a power supply rejection ratio of 44 dB is acquired. Comparing the main parameters of the proposed FMVR - to the state-of-the-art circuits - shows that it has higher efficiency with smaller area and lower power consumption.

Subthreshold reference circuit with curvature compensation based on the channel length modulation of MOS devices

AbstractA subthreshold nano‐power voltage and current reference with high‐order temperature compensation is proposed by taking advantage of the channel length modulation of MOS devices. Curvature compensation is implemented by providing proper compensating drain‐source voltages for the core devices of a first‐order CMOS reference such that the output nonlinear temperature factors can be compensated over a wide temperature range. In‐depth mathematical analysis is carried out to model the temperature dependency of the reference signals before and after compensation. As part of the analysis, Taylor expansion of the threshold voltage of MOS devices has been evaluated in a generalized fashion, enabling to clarify the complicated relationship between the high‐order temperature‐related terms of the output and design parameters. Simulated in a standard 0.18‐μm CMOS process, the minimum supply voltage of a proof‐of‐concept design is 1.0 V, providing 345 mV voltage reference with minimum temperature coefficient (TC) of 2.0 ppm/°C across the range of –40–140°C. The active area is 0.45 mm2 with around 200 nA current consumption. The DC line regulation is 0.23%/V, and the power supply rejection ratio (PSRR) is −63 dB at 10 Hz.

A CMOS PSR Enhancer with 87.3 mV PVT-Insensitive Dropout Voltage for Sensor Circuits.

A new power supply rejection (PSR) based enhancer with small and stable dropout voltage is presented in this work. It is implemented using TSMC-40 nm process technology and powered by 1.2 V supply voltage. A number of circuit techniques are proposed in this work. These include the temperature compensation for Level-Shifted Flipped Voltage Follower (LSFVF) and the Complementary-To-Absolute Temperature (CTAT) current reference. The typical output voltage and dropout voltage of the enhancer is 1.1127 V and 87.3 mV, respectively. The Monte-Carlo simulation of this output voltage yields a mean T.C. of 29.4 ppm/°C from −20 °C and 80 °C. Besides, the dropout voltage has been verified with good immunity against Process, Temperature and Process (PVT) variation through the worst-case simulation. Consuming only 4.75 μA, the circuit can drive load up to 500 μA to yield additional PSR improvement of 36 dB and 20 dB of PSR at 1 Hz and 1 MHz, respectively for the sensor circuit of interest. This is demonstrated through the application of an enhancer on the instrumentation Differential Difference Amplifier (DDA) for sensing floating bridge sensor signal. The comparative Monte-Carlo simulation results on a respective DDA circuit have revealed that the process sensitivity of output voltage of this work has achieved 14 times reduction in transient metrics with respect to that of the conventional counterpart over the operation temperature range in typical operation condition. Due to simplicity without voltage reference and operational amplifier(s), low power and small consumption of supply voltage headroom, the proposed work is very useful for supply noise sensitive analog or sensor circuit applications.

A Small Ripple and High-Efficiency Wordline Voltage Generator for 3-D nand Flash Memories

This article presents a small ripple and high-efficiency wordline (WL) voltage generator to supply voltage to the selected/unselected WLs for program and read operation in 3-D NAND Flash memories. With the proposed scheme of dynamic pump clock voltage and frequency scaling, the output ripple voltage can be minimized to reduce the variation of threshold voltage of the memory cells and the efficiency can be improved to save power consumption at the same time. What is more, with the minimized ripple, the requirement for power supply rejection ratio (PSRR) of the high-voltage regulator used to provide low noise WL voltage can be reduced. The proposed WL voltage generator has been fabricated in a 0.18- <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mu \text{m}$ </tex-math></inline-formula> triple-well CMOS process and the core chip size is 0.53 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> . While operating at a 1.8-V supply, the measurement results show that the ripple voltage is 5.5 mV at 12-V output voltage under the typical 50-pF cap load conditions of 3-D NAND Flash memories. Furthermore, the output ripple hardly varies with the increase of load current. In addition, the maximum power efficiency is 49% at 400 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mu \text{A}$ </tex-math></inline-formula> and can be maintained over 30% in the 50–450- <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mu \text{A}$ </tex-math></inline-formula> current load range.

Highly Efficient Fully Integrated Multivoltage-Domain Power Management With Enhanced PSR and Low Cross-Regulation

Multivoltage domains are urgently needed in modern system on chips (SoCs), while existing solutions such as switched dc−dc converter, switched capacitor converter, and low-dropout regulator (LDO) do not generate multivoltage domains conveniently and inexpensively. This article presents a highly efficient fully integrated power management strategy to provide the multiple voltage domains. The proposed architecture stacks a main LDO and several auxiliary push−pull regulators (APPRs) to generate multiple voltages for various loads in one SoC chip. The APPR regulates the load current by either absorbing or providing the additional current, which stabilizes the output voltages, increases the power supply rejection (PSR) and decreases the cross-regulation. A prototype with two output terminals is implemented with a standard 0.18- <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">μ</i> m CMOS technology. The whole system achieves high power efficiency of 96.5% and high PSR of −62 and −142 dB for upper and lower outputs, respectively. The chip area is 980 <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">μ</i> m × 500 <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">μ</i> m and the total quiescent current is 239 <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">μ</i> A. In addition, all off-chip components are eliminated, which is favorable for monolithic realization. The reduced system cost and the reduced electromagnetic interference also simplify the power management significantly, which helps to enable low-power and compact SoCs.

A Single BJT Bandgap Reference With Frequency Compensation Exploiting Mirror Pole

In this article, we propose a bandgap reference (BGR) with a single bipolar junction transistor (BJT) branch and a proportional-to-absolute-temperature (PTAT)-embedded amplifier. Having fewer BJT and passive components, the proposed BGR uses less power and area compared to the conventional BGR that uses multiple BJTs and resistors. As the proposed BGR achieves temperature compensation by employing a feedback loop that has two gain stages, frequency compensation is required. We propose frequency compensation scheme where a compensation capacitor is connected between the BGR output and a current mirror node in the PTAT-embedded amplifier. By using this scheme, location of a mirror pole associated with the current mirror node can be optimized to achieve both improved stability and low power consumption. Fabricated in 0.18- <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mu \text{m}$ </tex-math></inline-formula> CMOS, the proposed BGR achieves temperature coefficient of 26.3 ppm/°C over −40 °C–140 °C; voltage accuracy ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\sigma /\mu $ </tex-math></inline-formula> ) of 0.33%; and power supply rejection (PSR) of −52 dB, −44 dB at 100 Hz, 1 MHz respectively; while occupying 0.0082 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> and consuming 192 nW without startup circuit and trimming.

A 32-Channel Time-Multiplexed Artifact-Aware Neural Recording System.

This paper presents a low-power, low-noise microsystem for the recording of neural local field potentials or intracranial electroencephalographic signals. It features 32 time-multiplexed channels at the electrode interface and offers the possibility to spatially delta encode data to take advantage of the large correlation of signals captured from nearby channels. The circuit also implements a mixed-signal voltage-triggered auto-ranging algorithm which allows to attenuate large interferers in digital domain while preserving neural information. This effectively increases the system dynamic range and avoids the onset of saturation. A prototype, fabricated in a standard 180 nm CMOS process, has been experimentally verified in-vitro with cellular cultures of primary cortical neurons from mice. The system shows an integrated input-referred noise in the 0.5-200 Hz band of 1.4 μVrms for a spot noise of about 85 nV /√{Hz}. The system draws 1.5 μW per channel from 1.2 V supply and obtains 71 dB + 26 dB dynamic range when the artifact-aware auto-ranging mechanism is enabled, without penalising other critical specifications such as crosstalk between channels or common-mode and power supply rejection ratios.

64 dB Dynamic-Range 810 μW 90 MHz Fully-Differential Flipped-Source-Follower Analog Filter in 28nm-CMOS

This brief presents a 4 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">th</sup> -order continuous-time analog filter based on Flipped-Source-Follower stage. Source-Follower (SF) filters typically adopt pseudo-differential topology (critical for matching and bulk/substrate noise rejection) and are realized in not recent CMOS processes (130nm or 180nm) due to the intrinsic voltage headroom required by SF operation. The proposed device solves the above limitations by proposing a fully-differential circuital topology, which improves by 13 dB the power supply rejection with respect to pseudo differential approach, and by operating in 28nm-CMOS process, thanks to a proper level-shifter transistor, which enables optimum biasing point and enhances filter dynamic range. The prototype is composed by the cascade of two biquadratic cells. It features 90 MHz -3 dB bandwidth, and consumes 816 μW power (408 μW per cell) from a 1V supply. Dynamic-Range is 64 dB with 140 μV <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> RMS</sub> output noise, and at 0.32 V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">0-PEAK</sub> differential output voltage swing. Figure-of-Merit is 156 dBJ $^{-1}$ .

A Transimpedance-to-Noise Optimized Analog Front-End With High PSRR for Pulsed ToF Lidar Receivers

This paper presents a transimpedance-to-noise optimization approach for design of a resistive shunt-feedback TIA. This optimization offers an enhancement in the transimpedance and a noise performance very close to the theoretical minimum noise of the TIA. In addition, the transimpedance-to-noise optimization approach results in a small front-end FET size which enables a further reduction in power and area. Moreover, this approach enables using a fewer number of stages in the receiver chain which makes a high PSRR feasible and obviates the necessity for using an offset cancellation circuitry. Building on this approach, a fully differential analog front-end including a resistive shunt-feedback TIA and a post amplifier (PA) for time-of-flight (ToF) Lidar receivers is designed and implemented, achieving 94dB Ω transimpedance gain, 71nA input-referred rms noise current, -3dB bandwidth of 340MHz, and power supply rejection ratio (PSRR) of more than 87dB in a 0.11 μm CMOS process. The associated DC power consumption is 19.4mW with V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">DD</sub> of 1.8V. Moreover, a push-pull buffer with 1V output swing is integrated for driving 50 Ω loads, such as off-chip time discriminators, which also additionally amplifies the signal with a gain of 5dB while consuming an extra 20.9mW of DC power. The whole chip (excluding pads) occupies 210 μm × 110 μm in area.

High-PSRR Low-dropout Regulator with Fast Transient Response Time and Low Output Peak Voltage

This study proposes the feed-forward ripple cancellation (FFRC) technique to low drop-out (LDO) regulator. By adding load tracking impedance to the gate of pass transistor, it is possible to secure stability with a 100-nF capacitor having low ESR and be obtained less than 35 ㎱ response time. In all frequency bands, a power supply rejection ratio (PSRR) less than -70 ㏈ is obtained when the load current is 10 ㎃. The circuit is implemented in 65-㎚ CMOS process.

Unity-Gain Zero-Offset CMOS Buffer with Improved Feedforward Path

A voltage unity-gain zero-offset CMOS amplifier with reduced gain error and increased PSRR (power supply rejection ratio) is proposed. The amplifier uses two feed mechanisms, negative feedback and supporting positive feedforward, to achieve low deviation from unit gain over the entire input range. The circuit, designed in a standard 180-nanometer 1.8-voltage CMOS process, is compared with two known buffers of similar topology, also designed in the same process. Simulations show that, with the same supply (1.8 V), power (1.2 mW), load (12 pF), bandwidth (50 MHz), and similar area (600 µm2), the proposed buffer achieves the lowest gain error (0.3%) and the highest PSRR (72 dB).

A 42nA IQ , 1.5–6V VIN , Self-Regulated CMOS Voltage Reference With −93dB PSR at 10 Hz for Energy Harvesting Systems

This brief proposes a low-power voltage reference with low line sensitivity and high power supply rejection (PSR) under relatively wide supply voltage range. Excluding the small capacitors in start-up circuits, the proposed voltage reference is composed of only MOSFETs, most of which have been biased into the subthreshold region to achieve low power consumption. The self-regulating technique was also adopted to suppress the supply ripples and stabilize the supply voltage for the core reference circuits. The proposed reference circuit has been fabricated in 0.18- μm CMOS technology with a total chip area of 0.015 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> . When supply voltage is 1.5 V, the measured reference voltage is 985 mV and the total quiescent current is 42 nA. The measured temperature coefficient (TC) from -40°C to 85°C is 60.86 ppm/°C, while the line sensitivity is as low as 0.003 %/V over 1.5 ~ 6V supply range. Besides, the measured PSR is -93 dB and -57 dB, at 10 Hz and 1 MHz, respectively.

Design of high gain and high bandwidth operational transconductance amplifier (OTA)

ABSTRACT A novel operational transconductance amplifier (OTA) having high gain and high bandwidth for high-speed analog communication techniques and precision filtering is designed in this paper. The designed OTA uses β-multiplier-based current biasing scheme with folded cascode amplifier scheme in order to improve the small signal models and the DC gain of circuit. The OTA design was carried out using TSMC 65 nm CMOS technology using Cadence Virtuoso tool with 1 V supply voltage and 10 pf capacitive load. The output DC gain was found to be approximately 75.3 dB. In addition, the unity gain frequency for the designed OTA was found to be around 200 MHz. Superior common mode rejection ratio, power supply rejection ratio and slew rates along with compact chip area and low power are other salient features of the designed OTA. The designed OTA can be employed in order to design high performance analog circuits like data converters, phase-locked loops, etc.