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Abstract
A voltage unity-gain zero-offset CMOS amplifier with reduced gain error and increased PSRR (power supply rejection ratio) is proposed. The amplifier uses two feed mechanisms, negative feedback and supporting positive feedforward, to achieve low deviation from unit gain over the entire input range. The circuit, designed in a standard 180-nanometer 1.8-voltage CMOS process, is compared with two known buffers of similar topology, also designed in the same process. Simulations show that, with the same supply (1.8 V), power (1.2 mW), load (12 pF), bandwidth (50 MHz), and similar area (600 µm2), the proposed buffer achieves the lowest gain error (0.3%) and the highest PSRR (72 dB).
Highlights
A unity-gain buffer is an analogue amplifier with a voltage gain equal to 1 V/V. Among these amplifiers there are unity-gain zero-offset buffers characterized by zero offset between input and output voltages [1,2,3,4,5,6,7,8]
Unity-gain zero-offset buffers have found application in the testing of analogue chips [8], in analogue filtering [9,10,11], oscillators [12], voltage regulators [13,14], and in LCD panels [15,16]. Most of these buffer solutions use the classic approach based on a high-gain differential amplifier and a negative feedback to obtain unity gain and zero offset
A limitation of such a solution is the need for using an n-channel transistor without the body effect, which is not available in standard CMOS processes
Summary
A unity-gain buffer is an analogue amplifier with a voltage gain equal to 1 V/V. Among these amplifiers there are unity-gain zero-offset buffers characterized by zero offset between input and output voltages [1,2,3,4,5,6,7,8]. Unity-gain zero-offset buffers have found application in the testing of analogue chips [8], in analogue filtering [9,10,11], oscillators [12], voltage regulators [13,14], and in LCD panels [15,16] Most of these buffer solutions use the classic approach based on a high-gain differential amplifier and a negative feedback to obtain unity gain and zero offset. A representative example of the classic approach is the Miller opamp (operational amplifier) with an output connected to an inverting input (Figure 1a) The advantages of this buffer solution are its relatively simple design, wide input voltage range, and its full compatibility with standard CMOS technologies. To further reduce the gain error, it was proposed in [1] to use a common-mode signal In this case, a common-mode signal component is forwarded from the input to the output along an additional path. The gain error in (7) can be relatively small because the product |A1D·A2| ranges fromT1h0e2 gtoai1n0e3,rrdoerpiennd(7in) gcaonnbIBeIAreSlaantidvetlryanssmisatlolrbseizcaeus.se the product |A1D · A2| ranges from 102 to 103, depending on IBIAS and transistor sizes
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