Abstract
This paper presents a novel sub-1-V CMOS voltage reference with high power supply rejection ratio (PSRR), low line sensitivity, and low supply voltage. CMOS voltage references available in the literature use a self-biased cascode branch consisting of two MOS transistors operating in the subthreshold region to generate the proportional-to-absolute-temperature (PTAT) voltage only, whereas extra circuitry is required to generate the complementary-to-absolute-temperature (CTAT) voltage for temperature compensation. But in the proposed sub-1-V CMOS voltage reference, both the PTAT and CTAT voltages are generated using a single self-biased cascode branch. Two operational amplifiers in negative feedback topology are used to convert the PTAT and CTAT voltages into PTAT and CTAT currents, respectively, which help to enhance the stability and PSRR of the proposed voltage reference. The proposed voltage reference has been designed and simulated in 180-nm standard CMOS technology using Cadence Virtuoso Analog Design Environment. The proposed voltage reference achieves an output reference voltage of 424.85[Formula: see text]mV with a temperature coefficient of 29.5[Formula: see text]ppm/∘C for the temperatures ranging from [Formula: see text]C to 125∘C at a supply voltage of 0.8[Formula: see text]V. A line sensitivity of 0.0035%/V is achieved for the supply voltage varying from 0.8[Formula: see text]V to 5[Formula: see text]V at nominal temperature (27∘C). A PSRR of [Formula: see text]91.69[Formula: see text]dB is observed for the frequencies ranging from 1[Formula: see text]Hz to 10[Formula: see text]kHz at nominal conditions without using any capacitive filter. Also, the output noises of the proposed design at nominal conditions for the frequencies of 1[Formula: see text]Hz and 10[Formula: see text]kHz are obtained as 2.37[Formula: see text][Formula: see text]V/[Formula: see text]Hz and 45.26[Formula: see text]nV/[Formula: see text]Hz, respectively.
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