Buried P-layer Research Articles

Simulation study on single-event burnout reliability of 4H-SiC trench gate MOSFET with combined P-buried layer

In this article, the purpose of this numerical study is to investigate the rated 3.3-kV SiC power gate trench MOSFET structure with ground and float p-buried layer (DGF-MOS). The simulation results show the introduction of ground and float p-buried layer and upper drift layer optimized breakdown voltage (BV) the specific on-resistance (Ron,sp), and gate drain charge (Qgd,sp), thus the figure of merit (BV2/Ron,sp) is improved by 130 % and the figure of merit (Ron,sp × Qgd,sp) is reduced 173 % compared with the conventional SiC power gate trench MOSFET (CT-MOS). Additionally, the single-event burnout (SEB) simulation results show that the critical degradation threshold of CT-MOS structure is 900 V at LET = 0.5 pC/μm. The robustness of the DGF-MOS structure design to heavy ions was simulated. The results show that the maximum temperature peaks around the gate trench and substrate junction of the DGF-MOS structure could both be effectively suppressed due to the decrease in electric field peak. Consequently, the DGF-MOS structure showed a severe denaturation threshold of 1500 V, which was 66.6 % higher than that of the CT-MOS structure.

Novel Low Loss LIGBT With Assisted Depletion N-Region and P-Buried Layer

A novel low loss lateral insulated gate bipolar transistor (LIGBT) with high voltage level is designed and studied in this paper, and is proposed with assisted depletion N-region (AD) and P-buried layer (PB) in the bulk Si substrate, named PBAD LIGBT. The proposed PBAD LIGBT utilizes the idea of electric field modulation (EFM) to greatly improve the breakdown voltage, which optimizes the lateral and longitudinal electric field distribution by introduced high electric field peak. Therefore, compared with conventional (Conv.) LIGBT, the shortened drift length of proposed PBAD LIGBT is beneficial to improve the forward and switching characteristics at the same time, while maintaining the same breakdown characteristics. When the breakdown voltage reaches 360 V, according to the TCAD simulation results, the drift length of proposed PBAD LIGBT is <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$20{\mu }\text{m}$ </tex-math></inline-formula> , which is 71.4% shorter than that of Conv. LIGBT of <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$70{\mu }\text{m}$ </tex-math></inline-formula> . As a result of shortening drift length, the forward voltage drop and turn-off loss of proposed PBAD LIGBT are reduced by 51.4% and 68.5%, respectively. The simulated trade-off curves show that, proposed PBAD LIGBT achieves significantly improved trade-off performance between turn-off loss and forward voltage drop than that of Conv. LIGBT, including PB LIGBT and AD LIGBT.

Novel fast-switching LIGBT with P-buried layer and partial SOI* *Project supported by the National Basic Research Program of China (Grant No. 2015CB351906) and the Science Foundation for Distinguished Young Scholars of Shaanxi Province, China (Grant No. 2018JC-017).

A novel silicon-on-insulator lateral insulated gate bipolar transistor (SOI LIGBT) is proposed in this paper. The proposed device has a P-type buried layer and a partial-SOI layer, which is called the BPSOI-LIGBT. Due to the electric field modulation effect generated by the P-type buried layer and the partial-SOI layer, the proposed structure generates two new peaks in the surface electric field distribution, which can achieve a smaller device size with a higher breakdown voltage. The smaller size of the device is beneficial to the fast switching. The simulation shows that under the same size, the breakdown voltage of the BPSOI LIGBT is 26% higher than that of the conventional partial-SOI LIGBT (PSOI LIGBT), and 84% higher than the traditional SOI LIGBT. When the forward voltage drop is 2.05 V, the turn-off time of the BPSOI LIGBT is 71% shorter than that of the traditional SOI LIGBT. Therefore, the proposed BPSOI LIGBT has a better forward voltage drop and turn-off time trade-off than the traditional SOI LIGBT. In addition, the BPSOI LIGBT effectively relieves the self-heating effect of the traditional SOI LIGBT.

A Novel Ultralow R ON,sp Triple RESURF LDMOS With Sandwich n-p-n Layer

This article proposes a novel ultralow specific ON-resistance (RON,sp) triple reduced surface field (RESURF) lateral double-diffused MOSFET (LDMOS) with sandwich np-n layer. Compared with the conventional triple RESURF LDMOS with n-type top layer (NTTR LDMOS), the new structure is characterized by an additional N-buried layer below the P-buried layer. Due to the introduction of N-buried layer, the concentration of N-top layer will decrease to ensure charge balance, thus making the surface electric field distribution better and the higher additional doping introduced by N-top and N-buried layers can be achieved. The dose and implantation energy of n-p-n layers were simulated and optimized. Furthermore, in order to eliminate the premature avalanche breakdown occurring in the source-centered termination region, substrate termination technology (STT) is applied to avoid the high electric field peaks generated in the curved source region with small curvature radius. But the use of STT makes it easy to breakdown in the transitional region compared with the straight region. Therefore, the transitional region is studied and the crucial parameter AL in the layout of transitional region is also optimized. The fabricated device experimentally demonstrated improved performance with low R <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">ON,sp</sub> of 78.3 mΩ·cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> and high breakdown voltage (BV) of 795 V, and the experimental R <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">ON,sp</sub> is 26.8% lower than that of the conventional triple RESURF LDMOS (CTR LDMOS) and 10% lower than that of the NTTR LDMOS based on L <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">d</sub> = 67 μm, which can break the silicon limit of CTR and NTTR LDMOS and meet the demand of 700-V high-voltage integrated circuit applications.

Exploring SiC Planar IGBTs towards Enhanced Conductivity Modulation Comparable to SiC Trench IGBTs

The state-of-the-art silicon insulated-gate bipolar transistor (IGBT) features a trench gate, since it enhances the conductivity modulation. The SiC trench IGBT, however, faces the critical challenge of a high electric field in the gate oxide, which is a crucial threat to the device’s reliability. In this work, we explore the possibility of using a SiC planar IGBT structure to approach high performance to the level of a SiC trench IGBT, without suffering the high gate oxide field. The proposed SiC planar IGBT features buried p-layers directly under the p-bodies, and thus can be formed using the same mask set. The region between the buried p-layer and the p-body is heavily doped with n-type dopants so that the conductivity modulation is improved. Comprehensive TCAD simulations have been carried out to verify this concept, and the simulation results show the new SiC planar IGBT exhibits a high performance comparable to the trench IGBT, and also exhibits a low gate oxide field.

TCAD simulation of a breakdown-enhanced double channel GaN metal–insulator–semiconductor field-effect transistor with a P-buried layer

This paper proposes a new breakdown-enhanced gallium nitride (GaN) metal–insulator–semiconductor field-effect transistor (MISFET) with the architecture of a double channel and a P-buried layer, i.e. DCP-MISFET. The lower barrier and lower channel are connected to the drain, and the lower two-dimensional electron gas can improve the device electric field distribution between the gate and drain, achieving an enhanced breakdown voltage. At the same time, the P-buried layer below the gate field plate can reduce the peak electric field around the gate field plate. The proposed simulated device with LGD = 15 μm presents an excellent breakdown voltage of 2373 V. In addition, the ON-resistance of 15.07 s Ω mm and Baliga’s figure of merit of 3.736 GW cm−2 are achieved in the optimized DCP-MISFET. Compared with the breakdown voltage of 1547 V of the optimized field plate conventional GaN MISFET, the proposed device increases the breakdown voltage by 53.39% and the Baliga’s figure of merit is enhanced by 133.89%.

Improving breakdown voltage for 120 V level up shifter by using vertical and lateral assisted depletion layers in 0.35 μm CMOS technology

A novel isolation structure featuring a vertical assisted depletion layer (VADL) by p-buried layer (PBL) and lateral assisted depletion layer (LADL) by micro-n-well (μNW) for 120 V level up shifter is proposed. VADL and LADL efficiently prevents the premature breakdown of level shifter by fully depleting nLDMOS drain region and p-isolation (P-ISO) region respectively. By the effect of the electric field modulation, more uniform lateral and vertical electric fields are obtained due to the insertion of the VADL and LADL, which improves the breakdown voltage (BV) and device reliability. The breakdown and reliability mechanisms are investigated in detail by theoretical analysis, TCAD simulations and experimental measurements. The measured results shows, BV of 160 V and almost no HTRB degradation is seen after 168 h of stress. In addition, the new structure is fully compatible with standard 0.35 μm CMOS technology. Hence, it is not only a performance booster but also a low-cost solution.

Design and optimization of 30 V fully isolated nLDMOS with low specific on-resistance for HVIC applications

In this paper, a novel 30 V fully isolated n-channel lateral DMOS (nLDMOS) with low specific on-resistance (RON,sp) is proposed and experimentally realized using 0.35 µm Bipolar-CMOS-DMOS (BCD) process. We optimized the process parameters, such as doping concentration of the high-voltage drift n-well (HVNW) layer, P-buried layer (PBL) and pre deep n-well (Pre-DNW) layer, for achieving a superior tradeoff between high breakdown voltage (BV) and the low RON,sp. The proposed nLDMOS is fully isolated from the substrate to support negative bias to drain and has a very lower RON,sp than other competitors in the similar technology, which is critical for devices used in high-voltage, high-current switching applications such as HVIC's. The fabricated device exhibits a BV of 42 V with RON,sp as low as 15 mohm-mm2 . Besides, the new structure is fully compatible with standard 0.35 µm BCD technology, with a margin of up to 15% in process variation, which is large enough to meet the industrial requirement for mass production. Hence, it is not only high performance but also a low-cost solution.

Stacked lateral double-diffused metal-oxide-semiconductor field effect transistor with enhanced depletion effect by surface substrate**Project supported by the National Natural Science Foundation of China (Grant No. 61464003) and the Guangxi Natural Science Foundation, China (Grant Nos. 2015GXNSFAA139300 and 2018JJA170010).

A stacked lateral double-diffused metal–oxide–semiconductor field-effect transistor (LDMOS) with enhanced depletion effect by surface substrate is proposed (ST-LDMOS), which is compatible with the traditional CMOS processes. The new stacked structure is characterized by double substrates and surface dielectric trenches (SDT). The drift region is separated by the P-buried layer to form two vertically parallel devices. The doping concentration of the drift region is increased benefiting from the enhanced auxiliary depletion effect of the double substrates, leading to a lower specific on-resistance (Ron,sp). Multiple electric field peaks appear at the corners of the SDT, which improves the lateral electric field distribution and the breakdown voltage (BV). Compared to a conventional LDMOS (C-LDMOS), the BV in the ST-LDMOS increases from 259 V to 459 V, an improvement of 77.22%. The Ron,sp decreases from 39.62 mΩ·cm2 to 23.24 mΩ·cm2 and the Baliga’s figure of merit (FOM) of is 9.07 MW/cm2.

Area-Efficient and Snapback-Free SOI LIGBT With L-Shaped Extraction Path

A novel area-efficient snapback-free silicon-on-insulator lateral insulated gate bipolar transistor (SOI-LIGBT) is proposed and investigated for the first time in this paper. The device features an N+ anode, three separated P+ anodes, and a P-buried layer (PBL) in the N-buffer of the anode region. The N-buffer between all these components above forms a 3-D L-shaped extraction path. The L-shaped extraction path not only makes the device area-efficient but also increases the anode distributed resistance ( ${R} _{\mathrm{ SA}}$ ). Therefore, the snapback effect could be suppressed, and the tradeoff between the on-state voltage ( ${V} _{\mathrm{ on}}$ ) and turn-off energy ( ${E} _{\mathrm{ off}}$ ) is improved effectively. Simulation results show that the proposed device eliminates the snapback effect with 63% and 77% reduction of the anode region area compared with the segmented trenches in the anode region (STA) LIGBT and the separated shorted anode (SSA) LIGBT, respectively. At the same ${V} _{\mathrm{ on}}$ , the LEP LIGBT reduces the turn-off time ( ${t} _{\mathrm{ off}}$ ) and ${E} _{\mathrm{ off}}$ by 40% and 28%, respectively, compared with the STA LIGBT. Moreover, at the same ${E} _{\mathrm{ off}}$ , the LEP LIGBT reduces ${V} _{\mathrm{ on}}$ by 17%, compared with the SSA LIGBT.

Source engineering on ruggedness and RF performance of n-channel RFLDMOS

The state-of-art n-channel RFLDMOS (Radio Frequency Lateral Double-diffusion Metal Oxide Semiconductor) FETs with different source engineering have been fabricated using 0.18 μm BCD (Bipolar/COMS/DMOS) process. The ruggedness and RF performance of RFLDMOS have been studied with TLP (Transmission Line Pulse) test, VSWR (Voltage Stop Wave Ratio) test, and source/load-pull test. It was found that PBL (P+ buried layer) source engineering could improve its ruggedness remarkably. The mechanism of this improvement has been studied by introducing equivalent parasitic circuit. The dominant factor is the resistor RB which delays turn-on characteristic of parasitic NPN in equivalent circuit. And the computational model of RB is proposed. Furthermore, the optimal performance of RFLDMOS has also been discussed.

A novel superjunction lateral double-diffused MOS with segmented buried P-layer

A novel superjunction (SJ) lateral double-diffused MOS (LDMOS) with charge compensation to obtain an ultralow specific on-resistance (Ron,sp) is proposed in this paper. Segmented Buried P-layer(SBP)SJ LDMOS introduces segmented buried P-layer between the drift region and the substrate. The buried layer with gradual length from the source to the drain of SBP SJ LDMOS can also optimize the charge distribution of the drift region, which means it will reduce the charge compensation for SJ layer caused by the drift region under the source and increase the charge compensation for SJ layer caused by the drift region under the drain, thus achieving charge balance in the SJ layer. Compared with the conventional(Con.) SJ LDMOS at the same drift region of 33.5 μm, the breakdown voltage (BV) of the SBP SJ LDMOS is 680.5 V, enhanced by 41.7%. In addition, P-layer can also assist in depleting drift region to increase the concentrate of drift region and to decrease the Ron,sp of the device. When the gate voltage is 15 V, the Ron,sp is 42.8 mΩ cm2, reduced by 20.5% and the figure-of-merit(FOM) is 10.8 MW cm−2, increased by 152.8%.

A breakdown enhanced AlGaN/GaN MISFET with source-connected P-buried layer

This paper presents a breakdown-enhanced AlGaN/GaN MISFET with a source-connected P-buried layer combined with field plates (SC-PBL FPs MISFET). A TCAD tool was used to analyze the breakdown characteristics of the proposed structure, and results show that in comparison to the conventional gate field plate MISFET (GFP-C MISFET), the proposed structure provides a significant increase of breakdown voltage (VBK) due to redistribution of electric field in the gate-drain region induced by the SC-PBL and the FPs. The optimized SC-PBL FPs MISFET with a gate-drain spacing of 6 μm achieved a high Baliga’s figure of merit of 2.6 GW cm−2 with a corresponding breakdown voltage (VBK) of 1311.62 V and specific on resistance (RON,sp) of 0.66 mΩ cm2, which demonstrates a good trade-off between RON,sp and VBK compared to the GFP-C MISFET with VBK of 524.27 V and RON,sp of 0.61 mΩ cm2.

Ultralow Turn-OFF Loss SOI LIGBT With p-Buried Layer During Inductive Load Switching

An ultralow turn-OFF loss ( ${E} _{\mathrm{\scriptscriptstyle OFF}}$ ) silicon-on-insulator lateral insulated-gate bipolar transistor with a p-buried layer (PB SOI LIGBT) is first proposed. A universal ${E} _{\mathrm{\scriptscriptstyle OFF}}$ model during inductive load turn-OFF is set up, which reveals that low ${E} _{\mathrm{\scriptscriptstyle OFF}}$ can be achieved by reducing the total integral current charges, reducing the average anode voltage in the first phase and increasing the charge factor ${k}$ . Due to the large capacitance effect and extra hole extraction path induced by the PB, the three ideas for low ${E} _{\mathrm{\scriptscriptstyle OFF}}$ are demonstrated in the PB SOI LIGBT. Simulation results show that the PB SOI LIGBT can achieve an 85% lower ${E} _{\mathrm{\scriptscriptstyle OFF}}$ compared with the conventional SOI LIGBT based on 6- $\mu \text{m}$ SOI layer. Furthermore, the proposed ${E} _{\mathrm{\scriptscriptstyle OFF}}$ model can be applied to all the IGBTs, and it reveals the mechanism of low ${E} _{\mathrm{\scriptscriptstyle OFF}}$ of the IGBT with a superjunction structure during inductive load switching.

A novel low specific on-resistance double-gate LDMOS with multiple buried p-layers in the drift region based on the Silicon-On-Insulator substrate

A novel double-gate SOI LDMOS with multiple buried p-layers in the drift region (MBP SOI LDMOS) is proposed in this paper. MBP SOI LDMOS has two gates, the planar gate and the trench gate. The big feature of MBP LDMOS is the multiple buried p-layers with intervals in the drift region which is an arithmetic progression and decreases successively. Firstly, double gates of the structure form dual current conduction channels, leading to a low specific on-resistance (Ron,sp). Secondly, the multiple buried p-layers form a more significant triple RESURF effect, which not only increases the drift doping concentration but also modulates the electric field of the drift region, resulting in a low Ron,sp and a high breakdown voltage (BV). MBP SOI LDMOS is thus owning a reduced Ron,sp and an improved BV. The effects of structure parameters on the device performances are investigated. Compared with the conventional SOI LDMOS, the Ron,sp of MBP SOI LDMOS is reduced by 52.5% with BV increasing by 36.4% at the same 16-μm-drift region.

Influence of three-dimensional p-buried layer pattern on the performance of 4H-SiC floating junction Schottky barrier diode

4H-SiC floating junction Schottky barrier diodes (FJ-SBDs) are excellent SiC devices with high Baliga’s figure of merit (BFOM). However, the p-type buried layers in epilayers partially obstruct the current paths, and increase the on-resistance, while the buried layers of dot patterns can reduce the obstruction. In this paper, a three-dimensional (3D) simulation of 4H-SiC FJ-SBDs with dot patterns is reported for the first time. By comparing the results obtained from stripe, square, octagon, and circle patterns, dot patterns are proved to be good choices for buried layers in 4H-SiC FJ-SBDs, and the FJ-SBD with the circle pattern has the highest BFOM of 12.09 GW/cm2, which is 22.62% greater than that of the FJ-SBD with the stripe pattern.

Ultralow specific on-resistance high voltage trench SOI LDMOS with enhanced RESURF effect

A RESURF-enhanced high voltage SOI LDMOS (ER-LDMOS) with an ultralow specific on-resistance (Ron, sp) is proposed. The device features an oxide trench in the drift region, a P-pillar at the sidewall of the trench, and a buried P-layer (BPL) under the trench. First, the P-pillar adjacent to the P-body not only acts as a vertical junction termination extension (JTE), but also forms a vertical reduced surface field (RESURF) structure with the N-drift region. Both of them optimize the bulk electric field distributions and increase the doping concentration of the drift region. Second, the BPL together with the N-drift region and the buried oxide layer (BOX) exhibits a triple-RESURF effect, which further improves the bulk field distributions and the doping concentration. Additionally, multiple-directional depletion is induced owing to the P-pillar, the BPL, and two MIS-like structures consisting of the N-drift region combined with the oxide trench and the BOX. As a result, a significantly enhanced-RESURF effect is achieved, leading to a high breakdown voltage (BV) and a low Ron, sp. Moreover, the oxide trench folds the drift region in the vertical direction, resulting in a reduced cell pitch and thus Ron, sp. Simulated results show that the ER-LDMOS improves BV by 67% and reduces Ron, sp by 91% compared with the conventional trench LDMOS at the same cell pitch.

TC-LIGBTs on the Thin SoI Layer for the High Voltage Monolithic ICs With High Current Density and Latch-Up Immunity

A new 700 V tridimensional channel-lateral insulated-gate bipolar transistor (TC-LIGBT) structure on 1.5-μm-thin silicon on insulator (SoI) layer is presented in detail in this paper. There are numerous separated p-body cells located in the emitter region of the investigated TC-LIGBT, which can increase the efficient channel width, enhance electron injection, and attain a large current capability. By optimizing the doping of the middle doped n-type region between the adjacent p-body cells, a large current density of 568 A/cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> at VGE = 10 V, VCE = 20 V can be achieved, which has an improvement of 118% compared with the conventional SoI-LIGBT structure on the same thin SoI layer. To improve the latch-up capability, a highly doped p-buried layer has also been formed underneath the emitter region using 450-keV high-energy ion implantation. In this way, the proposed new TC-LIGBT can achieve almost the same latch-up immunity capability as with the conventional SoI-LIGBT structure.

A 700- V Junction-Isolated Triple RESURF LDMOS With N-Type Top Layer

A junction-isolated triple RESURF (JITR) LDMOS with high breakdown voltage (BV) and low specific on-resistance (R on,sp ) is proposed in this letter. Compared with the conventional triple RESURF (CTR) LDMOS, the new structure features a highly doped n-type top (N-top) layer at the surface of N-well, providing a low on-resistance surface conduction path in the on-state. The experimental result demonstrates that low R on,sp and high BV of above 730 V are achieved by the JITR LDMOS. R on,sp of the JITR LDMOS is about 15%-24.3% lower than that of the CTR LDMOS. The JITR LDMOS with horizontal N-top layer and P-buried layer resembles a super junction (SJ) LDMOS. Compared with the reported SJ LDMOS, the SJ layer of JITR LDMOS is formed in the longitudinal direction instead of the width direction, and the proposed JITR LDMOS exhibits almost the highest BV and high power figure of merit (FOM, defined as BV 2 /R on,sp ) in comparison to the published SJ LDMOS.

RESURF p-n Diode With a Buried Layer, a Comprehensive Study

In this paper, important parameters of the p-buried layer of a high-voltage reduced surface field p-n diode are analyzed and discussed in terms of effects on device performance, including breakdown voltage and specific turn-on resistance, Ron,sp. Guidelines for optimizing the vertical position, lateral location, and doping concentration of the p-buried layer are suggested. The experimental results demonstrate that the p-n diode with the proposed p-buried layer optimization design can improve breakdown voltage by 30.7% but only increases 2.7% in specific on-resistance Ron,sp.