Ultralow specific on-resistance high voltage trench SOI LDMOS with enhanced RESURF effect

Abstract

A RESURF-enhanced high voltage SOI LDMOS (ER-LDMOS) with an ultralow specific on-resistance (Ron, sp) is proposed. The device features an oxide trench in the drift region, a P-pillar at the sidewall of the trench, and a buried P-layer (BPL) under the trench. First, the P-pillar adjacent to the P-body not only acts as a vertical junction termination extension (JTE), but also forms a vertical reduced surface field (RESURF) structure with the N-drift region. Both of them optimize the bulk electric field distributions and increase the doping concentration of the drift region. Second, the BPL together with the N-drift region and the buried oxide layer (BOX) exhibits a triple-RESURF effect, which further improves the bulk field distributions and the doping concentration. Additionally, multiple-directional depletion is induced owing to the P-pillar, the BPL, and two MIS-like structures consisting of the N-drift region combined with the oxide trench and the BOX. As a result, a significantly enhanced-RESURF effect is achieved, leading to a high breakdown voltage (BV) and a low Ron, sp. Moreover, the oxide trench folds the drift region in the vertical direction, resulting in a reduced cell pitch and thus Ron, sp. Simulated results show that the ER-LDMOS improves BV by 67% and reduces Ron, sp by 91% compared with the conventional trench LDMOS at the same cell pitch.