Ultralow Turn-OFF Loss SOI LIGBT With p-Buried Layer During Inductive Load Switching

Abstract

An ultralow turn-OFF loss ( ${E} _{\mathrm{\scriptscriptstyle OFF}}$ ) silicon-on-insulator lateral insulated-gate bipolar transistor with a p-buried layer (PB SOI LIGBT) is first proposed. A universal ${E} _{\mathrm{\scriptscriptstyle OFF}}$ model during inductive load turn-OFF is set up, which reveals that low ${E} _{\mathrm{\scriptscriptstyle OFF}}$ can be achieved by reducing the total integral current charges, reducing the average anode voltage in the first phase and increasing the charge factor ${k}$ . Due to the large capacitance effect and extra hole extraction path induced by the PB, the three ideas for low ${E} _{\mathrm{\scriptscriptstyle OFF}}$ are demonstrated in the PB SOI LIGBT. Simulation results show that the PB SOI LIGBT can achieve an 85% lower ${E} _{\mathrm{\scriptscriptstyle OFF}}$ compared with the conventional SOI LIGBT based on 6- $\mu \text{m}$ SOI layer. Furthermore, the proposed ${E} _{\mathrm{\scriptscriptstyle OFF}}$ model can be applied to all the IGBTs, and it reveals the mechanism of low ${E} _{\mathrm{\scriptscriptstyle OFF}}$ of the IGBT with a superjunction structure during inductive load switching.