A low turnoff loss SOI LIGBT with p-buried layer and double gates

Yi-Tao He,Ming Qiao,Bo Zhang,Zhuo Wang Zhuo Wang,Zhao-Ji Li

doi:10.1109/icsict.2016.7998660

A low turnoff loss SOI LIGBT with p-buried layer and double gates

Yi-Tao He, Ming Qiao + Show 3 more

https://doi.org/10.1109/icsict.2016.7998660

Copy DOI

Publication Date: Oct 1, 2016

Citations: 2

Affiliation: National Engineering Research Center of Electromagnetic Radiation Control Materials, University of Electronic Science and Technology of China

#Low Turnoff Loss #SOI LIGBT + Show 8 more

Abstract
Full-Text PDF
Similar Papers

Abstract

A low turnoff loss (Eoff) silicon-on-insulator lateral insulated gate bipolar transistor with p-buried layer and double gates (DG-PB SOI LIGBT) is proposed. The proposed LIGBT features a p-buried layer (PB) in the n-drift region and an additional trench gate. Due to the large capacitance effect and hole extraction path induced by PB, larger number of the carriers is removed under low anode voltage (VA), which contributes to a fast turnoff and low turnoff loss (Eoff). What's more, the double gates (DG) structure can reduce the overall stored carriers in the on-state, further improving the Eoff ∼ Von tradeoff. Simulation results show that the DG-PB SOI LIGBT can achieve an 83 % lower Eoff compared with the conventional SOI LIGBT at the same Von of 1.05 V.

Full Text