Area-Efficient and Snapback-Free SOI LIGBT With L-Shaped Extraction Path

Abstract

A novel area-efficient snapback-free silicon-on-insulator lateral insulated gate bipolar transistor (SOI-LIGBT) is proposed and investigated for the first time in this paper. The device features an N+ anode, three separated P+ anodes, and a P-buried layer (PBL) in the N-buffer of the anode region. The N-buffer between all these components above forms a 3-D L-shaped extraction path. The L-shaped extraction path not only makes the device area-efficient but also increases the anode distributed resistance ( ${R} _{\mathrm{ SA}}$ ). Therefore, the snapback effect could be suppressed, and the tradeoff between the on-state voltage ( ${V} _{\mathrm{ on}}$ ) and turn-off energy ( ${E} _{\mathrm{ off}}$ ) is improved effectively. Simulation results show that the proposed device eliminates the snapback effect with 63% and 77% reduction of the anode region area compared with the segmented trenches in the anode region (STA) LIGBT and the separated shorted anode (SSA) LIGBT, respectively. At the same ${V} _{\mathrm{ on}}$ , the LEP LIGBT reduces the turn-off time ( ${t} _{\mathrm{ off}}$ ) and ${E} _{\mathrm{ off}}$ by 40% and 28%, respectively, compared with the STA LIGBT. Moreover, at the same ${E} _{\mathrm{ off}}$ , the LEP LIGBT reduces ${V} _{\mathrm{ on}}$ by 17%, compared with the SSA LIGBT.