Improving breakdown voltage for 120 V level up shifter by using vertical and lateral assisted depletion layers in 0.35 μm CMOS technology

Abstract

A novel isolation structure featuring a vertical assisted depletion layer (VADL) by p-buried layer (PBL) and lateral assisted depletion layer (LADL) by micro-n-well (μNW) for 120 V level up shifter is proposed. VADL and LADL efficiently prevents the premature breakdown of level shifter by fully depleting nLDMOS drain region and p-isolation (P-ISO) region respectively. By the effect of the electric field modulation, more uniform lateral and vertical electric fields are obtained due to the insertion of the VADL and LADL, which improves the breakdown voltage (BV) and device reliability. The breakdown and reliability mechanisms are investigated in detail by theoretical analysis, TCAD simulations and experimental measurements. The measured results shows, BV of 160 V and almost no HTRB degradation is seen after 168 h of stress. In addition, the new structure is fully compatible with standard 0.35 μm CMOS technology. Hence, it is not only a performance booster but also a low-cost solution.