Design and optimization of 30 V fully isolated nLDMOS with low specific on-resistance for HVIC applications

Abstract

In this paper, a novel 30 V fully isolated n-channel lateral DMOS (nLDMOS) with low specific on-resistance (RON,sp) is proposed and experimentally realized using 0.35 µm Bipolar-CMOS-DMOS (BCD) process. We optimized the process parameters, such as doping concentration of the high-voltage drift n-well (HVNW) layer, P-buried layer (PBL) and pre deep n-well (Pre-DNW) layer, for achieving a superior tradeoff between high breakdown voltage (BV) and the low RON,sp. The proposed nLDMOS is fully isolated from the substrate to support negative bias to drain and has a very lower RON,sp than other competitors in the similar technology, which is critical for devices used in high-voltage, high-current switching applications such as HVIC's. The fabricated device exhibits a BV of 42 V with RON,sp as low as 15 mohm-mm2 . Besides, the new structure is fully compatible with standard 0.35 µm BCD technology, with a margin of up to 15% in process variation, which is large enough to meet the industrial requirement for mass production. Hence, it is not only high performance but also a low-cost solution.